DPU IO Architect, Infrastructure Silicon

Meta Careers; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an experienced DPU I/O Architect to own the I/O subsystem for DPUs, defining hardware/software interfaces across registers, descriptors, and offload interfaces. You will collaborate with firmware, driver, and RTL teams to drive PV and bring-up, weighing performance, power, and area Trade-offs with data-backed decisions.

You will work on PCIe, DMA, I/O virtualization, and confidential computing, while shaping how hardware presents itself to firmware and software.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field.
• 8+ years architecting I/O and system subsystems hardware/software interfaces for NIC/DPU or ASICs.
• Experience with PCIe data link and transport protocols and I/O virtualization tech (SR-IOV, SIOV).
• Experience with cryptography concepts and inline data encryption.
• Experience with x86/ARM architectures, virtualization, IOMMUs, and interrupt virtualization.

Responsibilities

• Own the I/O subsystem architecture for DPUs including PCIe, DMA, offload engines, I/O virtualization, confidential computing, and system management from concept to silicon bring-up.
• Define hardware/software interfaces—registers, programming models, descriptors, doorbells, and offload interfaces.
• Collaborate with firmware, driver, and software teams to ensure clean, efficient interfaces and evolution with needs.
• Evaluate performance, power, and area trade-offs with data-backed rationale; support DV and PD toward reliable PV.

Skills

PCIe

DMA

IO virtualization

Confidential Computing

System management

Register and programming models

Descriptor/doorbell interfaces

Offload interfaces

x86/ARM architecture

IOMMU/interrupt virtualization

Cryptography concepts

AES-XTS/AES-GCM

Education

Bachelor's degree in Computer Science or Electrical Engineering

PhD in Computer Science/Engineering (preferred)

Tools

SystemVerilog

VHDL

Python

Job description

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs.We are looking for a Data Processing Unit (DPU) I/O Architect to own the I/O subsystem and the hardware/software interface between our silicon and the software that drives it - PCIe, DMA and offload engines, I/O virtualization, Confidential Computing, and system management. You'll define how the hardware presents itself to firmware and software - the register and programming models, descriptor and doorbell interfaces, and offload interfaces - and decide what belongs in hardware versus firmware versus software. You'll work hand in hand with the firmware, driver, and RTL teams, and carry your designs from early path-finding through implementation and silicon bring-up.DPU IO Architect, Infrastructure Silicon Responsibilities:Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management - from early path-finding through silicon bring-upDecide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between themDefine the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build onWork closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs changeWeigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is neededWork closely with design, DV, and PD teams on feature definition and PPA tradeoffrefine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DVSupport Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the I/O subsystemMinimum Qualifications:Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICsExperience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rulesExperience with I/O virtualization technologies such as SR-IOV and SIOVExperience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data EncryptionExperience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughputExperience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM)Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualizationExperience with data center workloads and their I/O characteristicsExperience driving architectural decisions independently and influencing their direction through dataPreferred Qualifications:PhD in Computer Science, Computer Engineering or Electrical Engineering15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICsExperience designing PCIe endpoints and root complexesExperience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flowsExperience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysisExperience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designsExperience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPIExperience designing high-performance DMA engines and offload accelerators, such as for cryptography and compressionExperience with post-silicon performance validation and model-to-hardware correlation methodologiesUnderstanding of Confidential Computing use cases and the related PCIe protocols - Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)About Meta:Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].$178,000/year to $250,000/year + bonus + equity + benefitsIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.