Distinguished Silicon Architect

Cognichip; Redwood City (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Cognichip is looking for a Distinguished Silicon Architect in Redwood City, California to design agentic workflows and enable AI agents for chip design and verification. The role requires over 20 years of experience in chip design and verification, with strong expertise in SystemVerilog RTL and UVM, as well as proficiency in Python and various EDA tools. Responsibilities include engaging with customers, defining EDA tool usage, and developing agent workflows. This position presents an exciting opportunity to integrate advanced AI in the semiconductor industry.

Qualifications

• 20+ years of experience in Chip Design & Verification.
• Strong hands-on expertise in SystemVerilog RTL and UVM.
• Ability to clearly explain design tradeoffs and debugging strategies.

Responsibilities

• Engage with customers to understand their pain points.
• Encode chip-design expertise into reusable knowledge.
• Define EDA tool usage for agents in design processes.
• Design end-to-end agent workflows for chip-related tasks.
• Develop high-quality prompts for chip design and verification.

Skills

Chip Design & Verification

SystemVerilog RTL

UVM

Python

Tools

EDA tools

LangGraph

LangChain

AutoGen

CrewAI

Job description

Job Title

Distinguished Silicon Architect

Job Description

Design agentic workflows, prompts, and domain knowledge that enable AI agents to perform production-quality chip design and verification. This role focuses on encoding deep silicon expertise - microarchitecture, RTL, DV, and EDA workflows - into structured agent behaviors, playbooks, and tool-aware processes.

Key Responsibilities

• Customer Engagement, Domain Knowledge, Tool Enablement
• Engage with customers to understand their pain points
• Encode chip-design expertise (RTL/DV best practices, microarchitectural patterns, failure modes) into reusable, agent-consumable knowledge and playbooks.
• Define EDA tool usage for agents—when to run simulation, lint, CDC, synthesis, and STA, how to interpret results, and how to chain tools into reliable flows.
• Agent Workflow & Orchestration
• Design end-to-end agent workflows for chip design, verification, debugging, and iterative refinement using structured process graphs.
• Decompose complex silicon workflows into executable agent steps with clear inputs, outputs, and success criteria, including hierarchical and iterative patterns.
• Prompt Engineering & Agent Behavior
• Develop high-quality prompts covering specification, microarchitecture, RTL, verification, and debug.
• Define agent behavior models, guardrails, and few-shot examples that guide reasoning, assumption validation, and error handling in chip-design tasks.

Required Qualifications

• 20+ years of experience (Staff) across the key domains: Chip Design & Verification
• Digital IC, ASIC, or SoC design or verification, with strong hands‑on expertise in SystemVerilog RTL and UVM.
• Deep familiarity with lint, CDC/RDC, simulation, timing constraints, and STA, and a solid understanding of microarchitecture (pipelines, FIFOs, DMA, caches, interconnects).
• Ability to clearly explain design tradeoffs and debugging strategies.
• Agentic AI & Software Experience with LLM-based agent systems, prompt engineering, and workflow decomposition.
• Familiarity with agent orchestration frameworks such as LangGraph, LangChain, AutoGen, or CrewAI, or equivalent custom systems.
• Proficiency in Python and experience integrating external tools into automated workflows.