Applied AI Chip Design Engineer: Build End-to-End Agents

Architect Labs

Palo Alto (CA)

On-site

USD 180,000 - 260,000

Full time

12 hours ago
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Benefits offered by this job

Competitive salary & equity

Job summary

Architect is a frontier AI lab focused on custom silicon design. We seek a Technical Staff (Applied AI) to bridge chip design and frontier AI, translating deep hardware expertise into agentic systems that reason about, generate, and verify real silicon.

You will design AI agents for core chip-design tasks, own end-to-end workflows, and curate data with engineering judgment to ensure outputs meet high standards.

Qualifications

  • MS or PhD in Electrical Engineering, EECS, or closely related field.
  • Strong RTL design or Design Verification experience across full chip design flow.
  • Proficient in Python or TypeScript; able to build tooling and production-grade software.
  • Demonstrated ability to own ambiguous problems and prototype quickly.
  • Genuine interest in applying frontier AI to hardware; prior ML research not required.

Responsibilities

  • Design and build AI agents for core chip-design tasks.
  • Own end-to-end agent workflows including scaffolding, tool use, and evaluation harnesses.
  • Curate data, define evaluation criteria, and encode engineering judgment for model outputs.
  • Collaborate with ML research, post-training, and infra teams to generate reward signals and benchmarks.
  • Move fast in a 0→1 environment and translate challenges into deployable capabilities.

Skills

RTL design experience
Software engineering
Prototype development
Curiosity for AI
Communication skills

Education

MS or PhD in Electrical Engineering / EECS or related field

Tools

Python
TypeScript
EDA tooling

Job description

Architect is a frontier AI lab focused on custom silicon design. We seek a Technical Staff (Applied AI) to bridge chip design and frontier AI, translating deep hardware expertise into agentic systems that reason about, generate, and verify real silicon.

You will design AI agents for core chip-design tasks, own end-to-end workflows, and curate data with engineering judgment to ensure outputs meet high standards.

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