Principal CAD Engineer

Ampere Computing; Santa Clara (CA); On-site; USD 195,000 - 292,000; Full time

Benefits offered by this job

Health insurance

401K retirement plan

Unlimited flextime

Paid holidays

Job summary

Ampere Computing is seeking a Principal CAD Engineer to lead high-performance physical design across multiple projects. You will drive PPA optimization from synthesis to sign-off and develop robust design flows for advanced nodes.

We expect strong experience in low power techniques (UPF/CPF), scripting (Python/Tcl), and Cadence Genus/Innovus, with a track record of delivering chip-scale designs and scalable CAD infrastructure. Join a team delivering energy-efficient AI compute.

Qualifications

• Proven experience driving PPA optimization across physical design flows – from synthesis to sign-off at advanced technology nodes.
• Success in delivering block or chip-level designs with aggressive PPA targets.
• Experience in low power design and implementation techniques using UPF/CPF.
• Proficiency in hierarchical P&R, floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.).
• Proficient in scripting using Tcl, Perl, Python, Makefile, etc.
• Expertise in developing scalable CAD infrastructure and automation frameworks for PPA regressions.
• Familiar with chip-finishing and sign-off processes including metal-fill, spare-cells, DFM, boundary-cell insertion, etc.
• Experience with EDA tools such as Cadence Genus, Innovus, Mentor Calibre, etc.
• Excellent communication, analytical and debugging skills.
• Electrical or Computer Engineering - Bachelor’s degree & 8 years of related experience; or Master’s degree & 6 years; or PhD & 3 years

Responsibilities

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing Power, Performance and Area (PPA)
• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects
• Analyze the impact of technology and design changes on PPA at block and full chip level
• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability
• Debug flow issues and implement robust automation for scalable deployment across various advanced technologies and design teams

Skills

PPA optimization

Scripting (Python/Tcl/Perl)

CAD infrastructure

Team collaboration

Analytical skills

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Genus

Cadence Innovus

Mentor Calibre

Job description

About Ampere

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!

About the role:

We are looking for an experienced Principal CAD Engineer to join a small but growing Processor Design group, advancing the art of high-performance implementation and physical design. Ideal candidates will develop and maintain physical design flows for high performance designs and contribute to PPA related methodology changes across multiple projects and technology nodes.

What you’ll achieve:

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing Power, Performance and Area (PPA)


• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects


• Analyze the impact of technology and design changes on PPA at block and full chip level


• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability


• Debug flow issues and implement robust automation for scalable deployment across various advanced technologies and design teams

About you:

• Proven experience driving PPA optimization across physical design flows – from synthesis to sign-off at advanced technology nodes


• Success in delivering block or chip-level designs with aggressive PPA targets


• Experience in low power design and implementation techniques using UPF/CPF


• Proficiency in hierarchical P&R, floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.)


• Proficient in scripting using Tcl, Perl, Python, Makefile, etc


• Expertise in developing scalable CAD infrastructure and automation frameworks for PPA regressions


• Familiar with chip-finishing and sign-off processes including metal-fill, spare-cells, DFM, boundary-cell insertion, etc


• Experience with EDA tools such as Cadence Genus, Innovus, Mentor Calibre, etc


• Excellent communication, analytical and debugging skills


• Electrical or Computer Engineering - Bachelor’s degree & 8 years of related experience; or Master’s degree & 6 years; or PhD & 3 years

What we’ll offer:

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $195,000 and $292,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit highlights include:

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.


• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.


• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

Description

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!

About the role:

We are looking for an experienced Principal CAD Engineer to join a small but growing Processor Design group, advancing the art of high-performance implementation and physical design. Ideal candidates will develop and maintain physical design flows for high performance designs and contribute to PPA related methodology changes across multiple projects and technology nodes.

What you’ll achieve:

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing Power, Performance and Area (PPA)


• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects


• Analyze the impact of technology and design changes on PPA at block and full chip level


• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability


• Debug flow issues and implement robust automation for scalable deployment across various advanced technologies and design teams

About you:

• Proven experience driving PPA optimization across physical design flows – from synthesis to sign-off at advanced technology nodes


• Success in delivering block or chip-level designs with aggressive PPA targets


• Experience in low power design and implementation techniques using UPF/CPF


• Proficiency in hierarchical P&R, floorplanning, pin-assignment, clock-distribution, critical-signal handling, hierarchical abstractions (black-box, ILM, etc.)


• Proficient in scripting using Tcl, Perl, Python, Makefile, etc


• Expertise in developing scalable CAD infrastructure and automation frameworks for PPA regressions


• Familiar with chip-finishing and sign-off processes including metal-fill, spare-cells, DFM, boundary-cell insertion, etc


• Experience with EDA tools such as Cadence Genus, Innovus, Mentor Calibre, etc


• Excellent communication, analytical and debugging skills


• Electrical or Computer Engineering - Bachelor’s degree & 8 years of related experience; or Master’s degree & 6 years; or PhD & 3 years

What we’ll offer:

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $195,000 and $292,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit highlights include:

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.


• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.


• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.