Director of 3D Stacked Logic Design

Socket.dev; San Jose (CA); On-site; USD 250,000 - 300,000; Full time

Benefits offered by this job

Health insurance

401k Matching

Paid time off

Parental Leave

Education reimbursement

Job summary

SK hynix America in San Jose seeks a Director of 3D Stacked Logic Design to lead high-speed digital IP development for 3D-stacked DRAM and DFT. You will guide RTL design, verification with U.S.-based customers, and build IP infrastructure to enable DRAM-on-Logic configurations.

You will manage foundry verification, drive IP services, and collaborate with cross-functional teams to strengthen market leadership in memory technology.

Qualifications

• Bachelor's degree or higher in Electrical Engineering or related field.
• Experience in RTL design and implementation for memory-related IP.
• 8+ years in digital IP design, RTL, or memory-related projects.
• Strong English communication skills.

Responsibilities

• Lead design of high-speed digital IP for 3D-stacked DRAM with U.S. customers.
• Drive foundry verification and infrastructure setup for IP business.
• Ensure seamless IP integration in customer design environments.
• Strengthen DRAM-on-Logic leadership through advanced digital IP design.
• Co-design 3D-stacked DRAM logic die with U.S.-based customers.

Skills

RTL design

Verilog

VHDL

Memory controller

DFT/DFD

PPA analysis

English communication

Education

Bachelor’s degree in Electrical Engineering

Job description

About SK hynix America:

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model:

Onsite

Job Title: Director of 3D Stacked Logic Design

Office Location: San Jose, CA

Job Type: Full-Time

Work Model: Onsite

Job Summary:

This role leads the design and implementation of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT, driving co-development initiatives with U.S.-based customers to enable DRAM-on-Logic system configurations. Key responsibilities include managing foundry verification of service-ready IPs, establishing IP business infrastructure, and ensuring seamless integration within customer design environments. The position focuses on strengthening market leadership through advanced digital IP design and delivering comprehensive services that support the co-design of 3D-stacked DRAM logic dies.

Responsibilities:

• Lead the design of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT with U.S.-based customers (including RTL design to implementation).
• Drive foundry Verification of Service-Ready IPs and Infrastructure Setup for IP Business.
• Deliver Services to Ensure Seamless IP Integration in Customer Design Environments.
• Strengthen Leadership in the DRAM-on-Logic Era through advanced digital IP design for 3D-Stacked DRAM.
• Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
• Co-design of 3D-stacked DRAM Logic Die with U.S –based customers.
• Improve competitiveness through close engagement with customers in US.

Qualifications:

• Bachelor’s degree or higher in Electrical Engineering or a related discipline.
• Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
• 8+ years of relevant experience in the following areas:
• Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design
• Experience in memory controller
• Experience in memory Built-in Self Test(BIST), DRAM Design for Test(DFT) / Design for Debug(DFD)
• Deep understanding of PPA analysis and optimization, and physical design.
• Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

Benefits:

• Top Tier health insurance at no employee cost
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees

Compensation:

Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.

Pay Range

$250,000—$300,000 USD

Equal Employment Opportunity:

SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.

In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying:

• E-Verify Participation Poster (Bilingual English & Spanish)
• IER Right to Work Poster (English)
• IER Right to Work Poster (Spanish)