Director, Next-Gen Memory Subsystem Architecture

SK hynix America; San Jose (CA); On-site; USD 250,000 - 300,000; Full time

Benefits offered by this job

Health Insurance

Paid Time Off

401k Matching

FSA

Education Reimbursement

Donation Matching/Volunteering

Free Meals

Job summary

SK hynix America seeks a Director of Buffer & Memory Subsystem Architecture to lead HW/SW co-design for next-generation HBF-xPU systems in San Jose, CA. You will translate AI workload traces into architectural policies for caching, prefetching, and data movement, with a focus on memory controllers and performance modeling.

You will own architecture decisions, interface contracts, and system-level efficiency across hardware and software, driving latency and bandwidth improvements.

Qualifications

• 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures.
• Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and workload characterization.
• Proven HW/SW co-design experience translating AI workload, compiler/runtime behavior into memory hierarchy and data movement requirements.
• Experience owning system architecture decisions, interface definitions, and performance acceptance criteria across multiple components.
• Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and applications.
• Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC.

Responsibilities

• Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
• Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
• Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
• Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
• Validate architectural assumptions and provide data-driven insights for cross-functional decisions.
• Define HBF Memory Architecture and Policies.

Skills

Memory Controllers

Cache/Prefetch

SSD/Storage Controllers

Accelerator Memory systems

DMA/Data Movement

Tools

Python

C/C++

SystemC

Simulation Tools

Job description

SK hynix America seeks a Director of Buffer & Memory Subsystem Architecture to lead HW/SW co-design for next-generation HBF-xPU systems in San Jose, CA. You will translate AI workload traces into architectural policies for caching, prefetching, and data movement, with a focus on memory controllers and performance modeling.

You will own architecture decisions, interface contracts, and system-level efficiency across hardware and software, driving latency and bandwidth improvements.