Director of Buffer & Memory Subsystem Architecture

SK hynix America; San Jose (CA); On-site; USD 250,000 - 300,000; Full time

Benefits offered by this job

Health Insurance

Paid Time Off

401k Matching

FSA

Education Reimbursement

Donation Matching/Volunteering

Free Meals

Job summary

SK hynix America seeks a Director of Buffer & Memory Subsystem Architecture to lead HW/SW co-design for next-generation HBF-xPU systems in San Jose, CA. You will translate AI workload traces into architectural policies for caching, prefetching, and data movement, with a focus on memory controllers and performance modeling.

You will own architecture decisions, interface contracts, and system-level efficiency across hardware and software, driving latency and bandwidth improvements.

Qualifications

• 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures.
• Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and workload characterization.
• Proven HW/SW co-design experience translating AI workload, compiler/runtime behavior into memory hierarchy and data movement requirements.
• Experience owning system architecture decisions, interface definitions, and performance acceptance criteria across multiple components.
• Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and applications.
• Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC.

Responsibilities

• Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
• Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
• Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
• Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
• Validate architectural assumptions and provide data-driven insights for cross-functional decisions.
• Define HBF Memory Architecture and Policies.

Skills

Memory Controllers

Cache/Prefetch

SSD/Storage Controllers

Accelerator Memory systems

DMA/Data Movement

Tools

Python

C/C++

SystemC

Simulation Tools

Job description

Director of Buffer & Memory Subsystem Architecture

San Jose, CA

About SK hynix America:

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations.We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Work Model: Onsite

Job Title: Director of Buffer & Memory Subsystem Architecture
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite

Job Summary:

As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF-xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.

Responsibilities:

• Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment with headquarters and external partners.
• Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
• Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
• Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
• Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
• Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
• Define HBF Memory Architecture and Policies.

Qualifications:

• 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms.
• Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization, with the ability to translate complex workload traces into architectural policies.
• Proven HW/SW co-design experience, including the ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
• Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components.
• Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software.
• Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.
• Top Tier health insurance at no employee cost
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Free Breakfast/Lunch/Dinner provided to employees

Compensation:

Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.

Pay Range

$250,000 - $300,000 USD

SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.

In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying: