Director, Networking ASIC Front-End & RTL Design

Hewlett Packard Enterprise Company in; San Diego (CA); On-site; USD 250,000 - 420,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Director to lead the ASIC Design & Front-End Implementation organization responsible for delivering next-generation networking ASICs from architecture through tapeout and deployment.

You will collaborate with Architecture, Verification, Emulation, SDK/Software, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing to ensure design quality, on-time delivery, and scalable, production-ready implementation.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of ASIC development experience, including 8+ years leading engineering teams and managers.
• Expertise in RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows.
• Proven success delivering complex ASICs from concept through production.
• Strong cross-functional leadership, communication, and program execution skills.

Responsibilities

• Lead RTL design and microarchitecture teams delivering complex networking ASICs.
• Drive design execution from architecture through RTL completion with PPA targets.
• Establish design methodologies, coding standards, and best practices.
• Partner with Physical Design to achieve floorplanning, timing, and tapeout readiness.
• Collaborate across Architecture, Verification, Emulation, SDK, and Product teams.
• Lead reviews, risk assessments, and milestone tracking across programs.

Skills

RTL design

Microarchitecture development

Cross-functional leadership

Program execution

Mentoring engineers

Education

BS/MS in Electrical Engineering / Computer Engineering

Tools

Verilog

SystemVerilog

Synthesis

Timing closure

Job description

Hewlett Packard Enterprise is seeking a Director to lead the ASIC Design & Front-End Implementation organization responsible for delivering next-generation networking ASICs from architecture through tapeout and deployment.

You will collaborate with Architecture, Verification, Emulation, SDK/Software, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing to ensure design quality, on-time delivery, and scalable, production-ready implementation.