Digital Design Engineer, SoC Chassis

Meta; Austin (TX); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is seeking design engineers to contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will design, implement, and optimize low-power hardware accelerators and state-of-the-art SoCs that enable the next generation of innovative devices and hardware.

Collaborate with researchers and engineers to map algorithms onto hardware, and work with DV and PD leads to advance IP and subsystem integration.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 6+ years of experience as a hardware design engineer for production silicon shipped in volume.
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development.
• Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams.

Responsibilities

• Design, implement, and optimize low-power hardware accelerators and SoCs.
• Collaborate with researchers and engineers to map algorithms onto hardware.
• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Drive the IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads.
• Coordinate with verification, physical design, and design for test teams.

Skills

ASIC architecture

RTL coding

Micro-architecture

Design verification

Power analysis

Cross-functional communication

AI tools integration

Education

Bachelor's degree in Computer Science/Engineering

Job description

Summary:

Meta is seeking design engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Required Skills:

1. Contribute to ASIC digital µArchitecture and design
2. Assist in the performance/power analysis of the design and help meet power and performance targets
3. Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
4. Collaborate with adjacent teams such as Verification, Physical Design, and Design for Test
5. Develop micro-architecture, RTL coding, and design verification for complex IPs
6. Drive the IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
3. 6+ years of experience as a hardware design engineer for production silicon shipped in volume
4. Experience in digital design µArchitecture, RTL coding, and micro-architecture development
5. Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams

Preferred Qualifications:

Preferred Qualifications:

1. Experience with one or more infrastructure IP areas, such as clock generation, distribution, and power management
2. Exposure to subsystem-level implementation or integration, in any part of the flow from specification through RTL signoff
3. Interest in growing into an infrastructure IP and subsystem implementation role
4. Experience with microcontroller clusters
5. Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
6. Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
7. Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

Public Compensation:

$146,000/year to $209,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affinine Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].