Digital Design Engineer, Interconnect

Meta; Sunnyvale (CA); In loco; USD 178.000 - 250.000; Tempo pieno

Vantaggi offerti da questo lavoro

Bonus

Equity

Benefits

Descrizione del lavoro

Meta seeks a Digital Design Engineer to help design and optimize low-power accelerators, state-of-the-art SoCs and custom silicon solutions. You will collaborate with researchers and engineers to develop micro-architecture, implement RTL, and map algorithms onto hardware.

You will work with DV, Physical Design and Design-for-Test teams to drive IP/sub-system integration, improve performance and power targets, and contribute to interconnect and NoC fabric initiatives.

Competenze

• Bachelor's degree in CS/CE or equivalent practical experience.
• 8+ years of hardware design experience for production silicon.
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development.
• Ability to communicate design decisions to cross-functional teams (verification, PD, architecture).

Mansioni

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis to meet targets.
• Map algorithms onto hardware and specify IP/subsystems requirements.
• Collaborate with DV, Physical Design, and Design-for-Test teams.
• Develop micro-architecture, RTL coding, and design verification for IPs.
• Drive IP/sub-system micro-architecture and RTL design with DV/PD leads.

Conoscenze

Digital design µArchitecture

RTL coding

Micro-architecture development

Cross-functional collaboration

Formazione

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Strumenti

Interconnect configurator

Fabric/IP integration tooling

Descrizione del lavoro

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Digital Design Engineer, Interconnect Responsibilities:

• Contribute to ASIC digital µArchitecture and design
• Assist performance/power analysis of the design and help meet power and performance targets
• Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
• Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test
• Develop micro-architecture, RTL coding, and design verification for complex IPs
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
• Experience in digital design µArchitecture, RTL coding, and micro-architecture development
• Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams

Preferred Qualifications:

• Experience with interconnect configurator and generation flows, and technically leading or mentoring engineers across deliverables
• Experience collaborating with physical design and timing partners on interconnect implementation, including timing- and floorplan-aware microarchitecture, pipelining and repeater strategy, physical partitioning, clock- and power-domain crossings, and architecture versus physical implementation trade-offs to close frequency, area, and power targets
• Experience defining fabric architecture and microarchitecture, including topology, address mapping, ordering and coherency requirements, buffering, quality-of-service, arbitration, and virtual-channel schemes, with industry-standard interconnect and bus protocols, and performance modeling and traffic-driven latency and bandwidth budgeting correlated against RTL results
• Demonstrated experience developing interconnect/NoC/fabric IP from architecture specification through RTL delivery
• Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
• Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
• Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.