Digital Design Engineer, DFT

Analog Devices, Inc.; Dallas, Northern (TX, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Analog Devices, Inc. is seeking a Digital Design Engineer focused on DFT who will define and implement DFT architectures for ASIC/SoC projects. You will insert scan chains, run ATPG, and verify designs analytically and with simulations.

Collaboration with multiple teams is essential to deliver high-coverage, low-power, and low-test-time patterns. The role requires a Masters in EE/CE and at least 2 years of DFT experience, with proficiency in scripting and experience with Tessent tools.

Qualifications

• MS degree in Electrical/Computer Engineering or similar.
• 2 years of directly related ASIC/SoC DFT experience.
• Strong understanding of DFT architecture and planning.
• Hands-on scan insertion and ATPG tool experience.
• Hands-on experience with DFT compression insertion, on-chip clock control insertion.
• Gate-level simulation with zero delay and SDF.
• Good understanding of failure analysis.
• Scripting: Perl/Python/Tcl.
• Team-player with strong communication skills.

Responsibilities

• Define and implement DFT architectures and specifications.
• Support DFT insertion across multiple product lines.
• Develop high-coverage, low-power, and low-test-time scan patterns.
• Conduct pre/post-silicon verification and debugging.
• Collaborate with peer organizations to integrate DFT solutions.

Skills

DFT design

ATPG tools

Perl/Python/Tcl

Gate-level simulation

Team collaboration

Communication skills

IEEE 1149/JTAG knowledge

Education

MS in Electrical/Computer Engineering

Tools

Tessent DFT tools

Job description

## Digital Design Engineer, DFTApply: US, TX, Dallas, Tollway: Full time: Posted Today: R266601**About Analog Devices**Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.As a key member of the team, he/she will be responsible for:* DFT specifications, architecture and implementation using state-of-the-art methodologies and tools* Support various product lines for DFT insertion* Support various product lines for High Coverage, Low Power, Low Test Time scan patterns* Pre/Post silicon verification & debug* Work independently as well as in teamMinimum Qualifications* Masters of Science degree in Electrical Engineering, Computer Engineering or similar* 2 years of directly related experience in ASIC/SoC DFT* Good understanding of DFT architecture and planning* Hands on scan insertion and ATPG Tool experience* Hands on experience of DFT Compression Insertion, On-Chip Clock Control Insertion* Hands on experience of Gate-level simulation with zero delay and SDF* Good understanding of Failure Analysis* Scripting: Perl/Python/Tcl* Team-player: the ability to forge and maintain relationships with peer-organizations* Strong written and verbal communication skillsPreferred Qualifications* Experience with Tessent DFT tools* Good understanding of IEEE 1149 and JTAG* Experience with LBIST and MBIST* Experience with advanced DFT technologies like low power, SSN, Fault Grading.*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.**Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.**EEO is the Law: Notice of Applicant Rights Under the Law.*Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days