Digital ASIC Verification Engineer: SystemVerilog & UVM

SpaceX; Union Hill-Novelty Hill (WA); On-site; USD 125,000 - 175,000; Full time

Benefits offered by this job

Life insurance

Parental leave

Paid holidays

401(k) retirement plan

Stock options

Job summary

A leading aerospace manufacturer is seeking a Design Verification Engineer to work on cutting-edge ASICs for space-based applications. This role involves digital ASIC verification, developing test plans, and utilizing Python and MATLAB for automation. Ideal candidates should hold a Bachelor's degree in Electrical Engineering and have experience in design verification. Join a dynamic team at the forefront of technology that is expanding internet access globally through advanced satellite systems.

Qualifications

• 1+ years of experience with design verification and test bench development.
• Experience with verification methodologies such as UVM.
• Strong object-oriented programming knowledge.

Responsibilities

• Responsible for digital ASIC verification at block and system level.
• Develop SystemVerilog testbench infrastructure for testing designs.
• Automate test case generation using Python and MATLAB.

Skills

Design verification

SystemVerilog

Python

MATLAB

Problem-solving

Education

Bachelor's degree in electrical engineering, computer science or computer engineering

Tools

UVM

RTL design

Job description

A leading aerospace manufacturer is seeking a Design Verification Engineer to work on cutting-edge ASICs for space-based applications. This role involves digital ASIC verification, developing test plans, and utilizing Python and MATLAB for automation. Ideal candidates should hold a Bachelor's degree in Electrical Engineering and have experience in design verification. Join a dynamic team at the forefront of technology that is expanding internet access globally through advanced satellite systems.