DFT Verification Intern — AI-Driven Chip Testing

Rivian; Palo Alto (CA); On-site; USD 62,000 - 70,000; Full time

Job summary

Rivian offers internship opportunities optimized for students pursuing undergraduate or graduate studies in an accredited program. Eligibility requires active enrollment with a graduation date between December 2027 and 2029. The Spring Co-op runs Jan-Aug 2027 and is on-site for full-time work (40 hours/week).

No visa sponsorship is provided. Interns will develop a Design-for-Test verification framework for Rivian's Autonomy Processor, with reports at block and chip levels, using AI-assisted

Qualifications

• Pursuing a bachelor's, master's, or PhD in Electrical/Computer Engineering or Computer Science.
• Digital logic design experience.
• RTL coding in Verilog/VHDL/SystemVerilog.
• TCL or Python scripting experience.
• Familiar with EDA tools.

Responsibilities

• Create Block level and Chip level Verifications using Post-DFT RTL/Netlist.
• Run simulations based on test lists or patterns.
• Generate MBIST verification reports.
• Verify Analog IP tests (PVT, Serdes PHY, DDR PHY) and generate reports.
• Perform Scan/ATPG verification and test coverage reporting.

Skills

Digital Logic design

RTL Coding (Verilog/VHDL/SystemVerilog

TCL/Python Scripting

Design/Verification knowledge

EDA tools familiarity

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Masters preferred

Tools

EDA tools

Job description

Rivian offers internship opportunities optimized for students pursuing undergraduate or graduate studies in an accredited program. Eligibility requires active enrollment with a graduation date between December 2027 and 2029. The Spring Co-op runs Jan-Aug 2027 and is on-site for full-time work (40 hours/week).

No visa sponsorship is provided. Interns will develop a Design-for-Test verification framework for Rivian's Autonomy Processor, with reports at block and chip levels, using AI-assisted