AI-Driven ASIC Intern: Silicon Performance & Safety

Rivian; Palo Alto (CA); On-site; USD 128,943,000 - 146,136,000; Full time

Benefits offered by this job

Paid vacation

Paid sick leave

Medical insurance

Job summary

Rivian is seeking interns for its Spring Co-op program in Palo Alto, CA. You must be an undergraduate or graduate student with an expected graduation date between December 2027 and 2029 and available for the full spring term.

In this role you will evaluate AI tools for Silicon development, build C++/SystemC performance models, and create verification assets for ASICs in ISO 26262 compliant ADAS contexts.

Qualifications

• Must be currently pursuing a bachelors, masters, or PhD degree at an accredited university.
• Actively pursuing a degree closely related to Electrical or Computer Engineering.
• Fundamentals of Computer architecture.
• CPU and Memory hierarchy.
• C/Python coding skills.
• SystemVerilog language.

Responsibilities

• Experiment with AI tools for Silicon development and automate RTL generation, documentation, and bug localization.
• Build bit-accurate C++/SystemC models to validate throughput of neural network layers against golden ML frameworks like PyTorch.
• Create scalable UVM-based testbench components and automated regression scripts for high-complexity SoC integration.
• Architect and implement performance monitors for Interconnect/AXI interfaces to analyze real-time inference latency.
• Design automated verification collateral to simulate hardware-level faults and ensure ISO 26262 compliance.

Skills

C/Python coding

SystemVerilog

CPU & memory hierarchy

Computer architecture basics

Education

Pursuing degree in ECE or related

Tools

C++

SystemC

PyTorch

Job description

Rivian is seeking interns for its Spring Co-op program in Palo Alto, CA. You must be an undergraduate or graduate student with an expected graduation date between December 2027 and 2029 and available for the full spring term.

In this role you will evaluate AI tools for Silicon development, build C++/SystemC performance models, and create verification assets for ASICs in ISO 26262 compliant ADAS contexts.