DFT Strategy & TestMAX Solutions Lead

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 250,000 - 320,000; Full time

Job summary

Synopsys, Inc. is seeking a seasoned DFT expert to architect and deploy TestMAX-based DFT solutions for complex ASIC and SoC designs in Sunnyvale, CA.

You will lead comprehensive DFT strategies, collaborating with design, manufacturing, and R&D teams to enable scalable test architectures and silicon reliability. The role requires deep expertise across scan architectures, ATPG, IJTAG, and IEEE standard implementations, with a focus on driving adoption of reusable methodologies and signoff

Qualifications

• 15+ years in Semiconductor/EDA with DFT, ATPG, and manufacturing test methodologies.
• Proven experience architecting DFT solutions for large ASIC/SoC designs.
• Hands-on with Synopsys TestMAX DFT and TestMAX ATPG.

Responsibilities

• Define and drive DFT methodologies for next‑gen ASIC/SoC designs.
• Lead deployment of advanced DFT architectures including IEEE standards.
• Architect scalable test access and instrumentation networks using IJTAG/IEEE standards.
• Mentor engineers and influence product roadmaps and technical leadership.

Skills

DFT Architecture

ATPG

JTAG/IJTAG

Boundary Scan

IEEE 1149.1/1149.6/1687/1500

Embedded Instrument Access

RTL-to-GDSII knowledge

Scripting: Tcl/Python

Education

BS/MS in Electrical/Computer Engineering

Tools

Synopsys TestMAX

TestMAX ATPG

IJTAG Tools

Tcl/Python scripting

Job description

Synopsys, Inc. is seeking a seasoned DFT expert to architect and deploy TestMAX-based DFT solutions for complex ASIC and SoC designs in Sunnyvale, CA.

You will lead comprehensive DFT strategies, collaborating with design, manufacturing, and R&D teams to enable scalable test architectures and silicon reliability. The role requires deep expertise across scan architectures, ATPG, IJTAG, and IEEE standard implementations, with a focus on driving adoption of reusable methodologies and signoff