DFT Engineer

VGAI Solutions; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

VGAI Solutions seeks a Senior DFT Engineer to lead scan insertion and ATPG validation efforts within a 12‑month engagement. The role requires 8–12 years of hands-on DFT experience and expertise with industry tools such as Mentor Tessent and Synopsys DFT Compiler.

You will collaborate with design and verification teams, implement DFT methodologies, and drive testability from insertion through sign-off in an ASIC/SoC flow.

Qualifications

• 8–12 years of hands-on DFT engineering experience.
• Strong experience in DFT Scan Insertion.
• Hands-on experience with ATPG Validation.
• Strong understanding of DFT methodologies, scan architecture, and ATPG flows.
• Strong debugging and problem-solving skills.

Responsibilities

• Perform DFT Scan Insertion and support scan architecture implementation.
• Develop, execute, and validate ATPG flows and test patterns.
• Analyze and debug ATPG and DFT-related issues.
• Work with design and verification teams to resolve scan and testability issues.
• Support DFT implementation, validation, and sign-off activities.
• Apply industry-standard DFT methodologies throughout the ASIC/SoC design flow.

Skills

DFT engineering

Scan Insertion

ATPG validation

Debugging

Problem solving

Tools

Mentor Tessent

Synopsys DFT Compiler

Job description

We are seeking a Senior DFT Engineer with 8–12 years of relevant experience in DFT Scan Insertion and ATPG Validation. The ideal candidate will have strong hands‑on experience with industry‑standard DFT methodologies, scan architecture, ATPG flows, and DFT implementation.

The candidate should have practical experience working with Mentor Tessent (Siemens) and Synopsys DFT Compiler, along with a strong understanding of scan insertion, ATPG generation, validation, debugging, and DFT‑related issues.

Senior DFT Engineer – Scan Insertion & ATPG Validation

Duration: 12 Months

Experience: 8–12 Years

Key Responsibilities

• Perform DFT Scan Insertion and support scan architecture implementation.
• Develop, execute, and validate ATPG flows and test patterns.
• Analyze and debug ATPG and DFT‑related issues.
• Work with design and verification teams to resolve scan and testability issues.
• Support DFT implementation, validation, and sign‑off activities.
• Apply industry‑standard DFT methodologies throughout the ASIC/SoC design flow.

Required Qualifications

• 8–12 years of hands‑on DFT engineering experience.
• Strong experience in DFT Scan Insertion.
• Hands‑on experience with ATPG Validation.
• Strong understanding of DFT methodologies, scan architecture, and ATPG flows.
• Strong debugging and problem‑solving skills.