DFT Design Engineer for ML-Accelerated SoCs

OpenTalent; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Health insurance

RSUs

Sign-on bonus

401(k) matching

Paid time off

Parental leave

Job summary

Amazon is seeking a Design for Test (DFT) engineer in Austin, TX to define DFT architectures for cutting-edge nodes and work with PD and block designers to implement efficient solutions. You will code in Verilog/SystemVerilog and verify RTL while using ATPG/JTAG/MBIST tools to achieve high test coverage.

You will participate in silicon debug with ATE and system teams, communicating across disciplines to drive robust, cost-effective test strategies.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or related field.
• 5+ years of practical DFT experience with complex SoC designs in advanced nodes.
• Experience with ATPG, JTAG, MBIST; trade-offs between test quality and time.
• Experience with automation script development.

Responsibilities

• Define and develop state-of-the-art DFT architectures for advanced technology nodes.
• Collaborate with block designers and PD teams to implement efficient DFT solutions.
• Perform RTL coding and verification using Verilog/SystemVerilog.
• Use DFT tools to create high coverage test patterns for silicon defects.
• Participate in silicon debug with ATE and System teams.
• Communicate across disciplines to align on design-for-test goals.

Skills

DFT experience

Verilog/SystemVerilog

Automation scripting

RTL verification

Perl/Python/Tcl scripting

Team communication

Education

Bachelor's degree in Electrical or Communications Engineering

Master's degree (preferred)

Tools

ATPG tools

JTAG

MBIST

SDF gate-level timing tools

Job description

Amazon is seeking a Design for Test (DFT) engineer in Austin, TX to define DFT architectures for cutting-edge nodes and work with PD and block designers to implement efficient solutions. You will code in Verilog/SystemVerilog and verify RTL while using ATPG/JTAG/MBIST tools to achieve high test coverage.

You will participate in silicon debug with ATE and system teams, communicating across disciplines to drive robust, cost-effective test strategies.