DFT Design Engineer, Machine Learning Acceleration - Amazon Web Services

OpenTalent; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Health insurance

RSUs

Sign-on bonus

401(k) matching

Paid time off

Parental leave

Job summary

Amazon is seeking a Design for Test (DFT) engineer in Austin, TX to define DFT architectures for cutting-edge nodes and work with PD and block designers to implement efficient solutions. You will code in Verilog/SystemVerilog and verify RTL while using ATPG/JTAG/MBIST tools to achieve high test coverage.

You will participate in silicon debug with ATE and system teams, communicating across disciplines to drive robust, cost-effective test strategies.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or related field.
• 5+ years of practical DFT experience with complex SoC designs in advanced nodes.
• Experience with ATPG, JTAG, MBIST; trade-offs between test quality and time.
• Experience with automation script development.

Responsibilities

• Define and develop state-of-the-art DFT architectures for advanced technology nodes.
• Collaborate with block designers and PD teams to implement efficient DFT solutions.
• Perform RTL coding and verification using Verilog/SystemVerilog.
• Use DFT tools to create high coverage test patterns for silicon defects.
• Participate in silicon debug with ATE and System teams.
• Communicate across disciplines to align on design-for-test goals.

Skills

DFT experience

Verilog/SystemVerilog

Automation scripting

RTL verification

Perl/Python/Tcl scripting

Team communication

Education

Bachelor's degree in Electrical or Communications Engineering

Master's degree (preferred)

Tools

ATPG tools

JTAG

MBIST

SDF gate-level timing tools

Job description

DESCRIPTION

• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
• Perform RTL coding and Verification using Verilog/System Verilog
• Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects
• Participate in Silicon debug efforts alongside ATE and System teams
• Communicate and work with team members across multiple disciplines

BASIC QUALIFICATIONS

• Bachelor's degree in Electrical or Communications Engineering or a related field
• 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes
• Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience with automation script development

PREFERRED QUALIFICATIONS

• Master's degree in Electrical or Communications Engineering or a related field
• Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing
• Experience with RTL coding and design verification (DV) flows
• Experience with gate-level simulation setup and debug with SDF
• Strong programming and scripting skills in Perl, Python or Tcl
• Practical experience with silicon debug and yield optimization

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.