Device Engineer: Yield & Process Optimization

Onsemi; Gresham (KY); Presencial; USD 90 000 - 130 000; Tempo integral

Resumo da oferta

onsemi is seeking a highly motivated Engineer to join our Device Engineering / Yield Enhancement group in Gresham, OR. You will work with Engineers and Technicians in a fast-paced silicon wafer fab production and technology development environment, spanning from bare wafers to finished goods.

The role focuses on manufacturability and interfacing with Fab Process Engineering, Technology Development, Failure Analysis, Design/Layout, wafer probe/test, and quality teams.

Qualificações

• BS/MS or equivalent in Engineering, with BSEE/MSEE preferred.
• Broad understanding of semiconductor devices (CMOS, DMOS, Bipolars).
• 5+ years of experience in semiconductor process technology and wafer fabrication.
• Strong problem-solving mindset and data-driven decision making.
• Clear written and oral communication skills; strong interpersonal abilities.

Responsabilidades

• Yield enhancement for production products.
• New product introduction into the Fab.
• S scrap reduction and prevention.
• Process improvements using existing and new equipment, often with Process Engineering.
• Analyze manufacturing and test data to improve product performance.
• Ensure all shipped material meets requirements.
• Present trends, KPIs, and process improvements to management.

Conhecimentos

Problem-solving mindset

Data analysis & statistics

Written and oral communication

Interpersonal skills

Semiconductor device knowledge

Formação académica

BS/MS or equivalent in Engineering

Descrição da oferta de emprego

onsemi is seeking a highly motivated Engineer to join our Device Engineering / Yield Enhancement group in Gresham, OR. You will work with Engineers and Technicians in a fast-paced silicon wafer fab production and technology development environment, spanning from bare wafers to finished goods.

The role focuses on manufacturability and interfacing with Fab Process Engineering, Technology Development, Failure Analysis, Design/Layout, wafer probe/test, and quality teams.