Design Verification Engineering Intern - MS/PhD

Texas Instruments Incorporated; Dallas, Northern (TX, KY); Hybrid; USD 22,000 - 38,000; Full time

Job summary

Texas Instruments Incorporated is seeking a Design Verification intern to help shape future technologies in Dallas. You will develop detailed verification plans, build test benches, and run simulations to verify DUT behavior across mixed-signal domains.

You will track verification status, work with regression tools, and contribute to continuous improvements in DV strategy and flows, including timing checks between analog and digital circuits.

Qualifications

• Develop verification plans with design and system teams.
• Create test benches, tests and simulations for DUT behavior.
• Work with regression tools and scripts for regression analysis.

Responsibilities

• Communicate verification status and issues.
• Verify chip‑level timing between analog and digital circuits.
• Contribute to DV strategy improvements.

Skills

SystemVerilog

Test benches

Simulation

RTL design

Gates+SDF

Regression tools

Tools

Gates+SDF

Regression tools

Job description

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it.

As a Design Verification intern in this group, you will be responsible for:

• Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Put your talent to work with us as a Design Engineer Intern - change the world, love your job!