Design Verification Intern - Engineer the Future of Chips

Texas Instruments; Knoxville (TN); On-site; USD 28,000 - 41,000; Full time

Job summary

Texas Instruments in Knoxville, TN is seeking a Design Verification Intern to contribute to pre-silicon verification of mixed-signal circuits. You will help develop verification plans, test benches, tests, and simulations for DUT behavior.

You will run coverage regressions to meet goals, track verification status, and script regression tasks using regression tools and RTL/Gates+SDF, including timing checks between analog and digital.

Qualifications

• Pursuing graduate degree in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering.
• GPA of 3.0/4.0 or higher required for minimum qualification.

Responsibilities

• Develop detailed verification plans in collaboration with design and system teams.
• Create test benches, tests and simulations to verify DUT behavior.
• Run coverage regressions to meet SystemVerilog coverage goals for mixed-signal designs.
• Track and communicate verification status, issues and concerns across teams.
• Work with regression tools and scripts to submit regression cases.
• Utilize RTL and Gates+SDF, and verify chip-level timing between analog and digital domains.
• Apply constrained-random stimulus and auto-checking verification environments.
• Contribute to ongoing improvements in DV strategy, tools, methods and flows.

Skills

Strong communication

Stakeholder relationships

Team collaboration

Initiative & drive

Time management

Analytical thinking

Problem solving

Education

Graduate degree in EE/CE

GPA 3.0/4.0 or higher

Tools

Regression tools

RTL/Gates+SDF tools

Regression scripting

Job description

Texas Instruments in Knoxville, TN is seeking a Design Verification Intern to contribute to pre-silicon verification of mixed-signal circuits. You will help develop verification plans, test benches, tests, and simulations for DUT behavior.

You will run coverage regressions to meet goals, track verification status, and script regression tasks using regression tools and RTL/Gates+SDF, including timing checks between analog and digital.