Design Verification Engineer Intern: Build & Verify Chips

Texas Instruments Incorporated; Dallas, Northern (TX, KY); Hybrid; USD 35,000 - 52,000; Full time

Job summary

Texas Instruments invites a Design Verification Intern to contribute to pre-silicon verification efforts in a fast-paced team environment. You will develop verification plans, create test benches and simulations, and run coverage regressions to ensure robust DUT behavior across analog and digital domains.

You will also track verification status, use regression tools, and script automation to streamline analyses. The role emphasizes collaboration with design teams and continuous DV improvements.

Qualifications

• Proficient in pre-silicon verification planning and execution.
• Experience developing test benches and verification tests.
• Ability to run and interpret coverage regressions for functional coverage.
• Strong communication to track verification status and issues.
• Experience scripting to automate regression analysis workflows.
• Familiarity with RTL and timing checks between analog and digital domains.
• Knowledge of constrained-random stimulus for analog environments.
• Contribute to continuous improvements of DV tools and methods.

Responsibilities

• Develop detailed verification plans with design and system teams.
• Develop test benches, tests and simulations for DUT behavior.
• Run coverage regressions to meet coverage goals for SystemVerilog models.
• Track and communicate verification status, issues and concerns.
• Work with regression tools and scripts for regression analysis.
• Utilize RTL and Gates+SDF for chip-level timing verification.
• Use constrained-random verification for analog stimulus.
• Contribute to DV strategy improvements and tool flows.

Skills

SystemVerilog

Test benches

Regression tools

Scripting

RTL

Tools

Gates+SDF

Job description

Texas Instruments invites a Design Verification Intern to contribute to pre-silicon verification efforts in a fast-paced team environment. You will develop verification plans, create test benches and simulations, and run coverage regressions to ensure robust DUT behavior across analog and digital domains.

You will also track verification status, use regression tools, and script automation to streamline analyses. The role emphasizes collaboration with design teams and continuous DV improvements.