Design Verification Engineering Intern - Bachelors

Texas Instruments; Dallas (TX); On-site; USD 18,000 - 24,000; Full time

Job summary

Texas Instruments invites applications for a Design Verification intern in Dallas. You will develop verification plans, build test benches and run simulations to validate DUT behavior, and drive coverage regressions for SystemVerilog models across analog and digital domains.

You will track verification status, work with regression tools, and contribute to DV methods and flows. This internship emphasizes cross-functional collaboration with design and system teams.

Responsibilities

• Developing detailed verification plans while working closely with the design and system team to ensure pre-silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Skills

SystemVerilog

Test benches

Regression tooling

Scripting

Gates+SDF

Constrained-random

DV methodology

Tools

Gates+SDF

Job description

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it.

As a Design Verification intern in this group, you will be responsible for:

• Developing detailed verification plans while working closely with the design and system team to ensure pre-silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Put your talent to work with us as a Design Engineer Intern – change the world, love your job!

Texas Instruments will not sponsor job applicants for visas or work authorization for this position.