Design Verification Engineering Intern - Bachelors

Texas Instruments Incorporated; Dallas, Northern (TX, KY); Hybrid; USD 35,000 - 52,000; Full time

Job summary

Texas Instruments invites a Design Verification Intern to contribute to pre-silicon verification efforts in a fast-paced team environment. You will develop verification plans, create test benches and simulations, and run coverage regressions to ensure robust DUT behavior across analog and digital domains.

You will also track verification status, use regression tools, and script automation to streamline analyses. The role emphasizes collaboration with design teams and continuous DV improvements.

Qualifications

• Proficient in pre-silicon verification planning and execution.
• Experience developing test benches and verification tests.
• Ability to run and interpret coverage regressions for functional coverage.
• Strong communication to track verification status and issues.
• Experience scripting to automate regression analysis workflows.
• Familiarity with RTL and timing checks between analog and digital domains.
• Knowledge of constrained-random stimulus for analog environments.
• Contribute to continuous improvements of DV tools and methods.

Responsibilities

• Develop detailed verification plans with design and system teams.
• Develop test benches, tests and simulations for DUT behavior.
• Run coverage regressions to meet coverage goals for SystemVerilog models.
• Track and communicate verification status, issues and concerns.
• Work with regression tools and scripts for regression analysis.
• Utilize RTL and Gates+SDF for chip-level timing verification.
• Use constrained-random verification for analog stimulus.
• Contribute to DV strategy improvements and tool flows.

Skills

SystemVerilog

Test benches

Regression tools

Scripting

RTL

Tools

Gates+SDF

Job description

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it.

As a Design Verification intern in this group, you will be responsible for:

• Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Put your talent to work with us as a Design Engineer Intern – change the world, love your job!

Texas Instruments will not sponsor job applicants for visas or work authorization for this position.