Lead Formal Verification Engineer - AI Accelerator Silicon

Acceler8 Talent; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is partnering with an early-stage AI hardware startup to hire a Formal Verification Engineer to own the verification strategy for AI accelerator silicon, from block- to SoC-level, ensuring correctness of complex hardware.

You will write SystemVerilog Assertions (SVA), develop formal environments, debug proof failures with RTL designers, and help define next-generation AI-assisted verification methodologies alongside architecture, RTL and software teams.

Qualifications

• Masters degree (or equivalent) plus 8+ years in formal verification.
• Deep expertise in formal verification methodologies, including property authoring (SVA and/or PSL), proof strategies, abstraction techniques, and convergence.
• Strong experience debugging formal failures and working directly with RTL designers to resolve issues.
• Hands-on experience with industry-standard formal verification tools such as Synopsys VC Formal, Cadence JasperGold, or equivalent.
• Strong understanding of modern digital design and microarchitecture.

Responsibilities

• Own block- and SoC-level formal verification for AI accelerator silicon, from property development through proof convergence.
• Develop SystemVerilog Assertions (SVA) and formal verification environments to verify complex microarchitectural and system-level behavior.
• Debug proof failures, identify root causes, and collaborate with RTL designers and architects to drive closure.
• Build and improve formal verification methodologies, infrastructure, and AI-assisted verification flows, including AI agents that accelerate proof generation and convergence.
• Apply formal techniques throughout the development cycle, from early architectural validation through silicon bring-up readiness.
• Partner closely with design, verification, and software teams to ensure robust, scalable hardware.

Skills

Formal verification

SVA/PSL

Debugging

VC Formal/JasperGold

Education

Master's degree in Electrical/Computer Engineering or related field

Tools

Synopsys VC Formal

Cadence JasperGold

Job description

Acceler8 Talent is partnering with an early-stage AI hardware startup to hire a Formal Verification Engineer to own the verification strategy for AI accelerator silicon, from block- to SoC-level, ensuring correctness of complex hardware.

You will write SystemVerilog Assertions (SVA), develop formal environments, debug proof failures with RTL designers, and help define next-generation AI-assisted verification methodologies alongside architecture, RTL and software teams.