Design Verification Engineer

Tara Technical Solutions (TTS); San Jose (CA); On-site; USD 130,000 - 192,000; Full time

Benefits offered by this job

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Child care support

Pension plan

Paid paternity leave

Student loan assistance

Disability insurance

Tuition assistance

Job summary

A leading semiconductor firm in San Jose is seeking a Design Verification Engineer responsible for verifying complex designs. The ideal candidate will have significant experience designing test benches and a strong grasp of verification methodologies like UVM. A Bachelor's degree with relevant experience is required. Competitive salary and benefits are offered, including health insurance and 401(k).

Qualifications

• Expertise in architecting reusable and constrained random test benches from scratch.
• Strong understanding of System Verilog assertions.

Responsibilities

• Responsible for verification from test planning to functional/code coverage closure.
• Conduct verification on complex designs and IP interfaces.

Skills

Expertise in architecting reusable and constrained random test benches

Expertise in verification methodologies like UVM

Verification expertise with Interface IP designs

Experience with ARM based bus protocols

Strong understanding of System Verilog assertions

Education

Bachelor's Degree + 8+ years of experience

Master's Degree + 6+ years of experience

Job description

Tara Technical Solutions (TTS) provided pay range

This range is provided by Tara Technical Solutions (TTS). Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$130,000.00/yr - $192,000.00/yr

Direct message the job poster from Tara Technical Solutions (TTS)

Tara Technical Solutions Recruiting- 24 Years of Semiconductor Recruiting.

Functional verification of complex designs.

Responsible for verification from test planning, test bench development, test execution and functional/code coverage closure.

Skills/Expertise:

Expertise in architecting reusable and constrained random test benches from scratch.

Expertise in verification methodologies like UVM.

Verification expertise with Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes designs.

Experience with ARM based bus protocols like APB, AXI and CHI is highly desirable.

Strong understanding of System Verilog assertions and ability to quickly write effective coverage and assertion properties.

Minimum Industry Experience :

Bachelor's Degree + 8+ years of related experience;

OR

Master's Degree + 6+ years of experience.

Having Exp in Memory Controllers And Or HBM or Ethernet/MAC is also a PLUS.

* H1B Transfer IS NOT open at this time.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Design

• Industries

  Semiconductor Manufacturing

Referrals increase your chances of interviewing at Tara Technical Solutions (TTS) by 2x

Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

Paid maternity leave

Child care support

Pension plan

Paid paternity leave

Student loan assistance

Disability insurance

Tuition assistance

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