Design Verification Engineer

Chiparama; Austin (TX); On-site; USD 114,000 - 213,000; Full time

Job summary

Chiparama seeks a mid-senior level Design Verification Engineer based in Austin, TX, to join their dynamic design verification team. You'll work collaboratively to test RTL modules, develop verification components, and leverage industry-leading methodologies for verification in a stimulating environment. This role offers a unique opportunity to impact machine learning acceleration hardware projects while utilizing your expertise in System Verilog and UVM.

Qualifications

• Typically requires minimum of 5-15 years of experience.
• Strong knowledge of design & verification methodologies.
• Hands on experience in System Verilog, UVM, and C/C++.

Responsibilities

• Test RTL modules using UVM and develop reusable verification components.
• Collaborate with logic designers and ensure on-time delivery of layouts.
• Develop test environments and plans for code coverage.

Skills

System Verilog

UVM

C/C++

RTL

Verification methodologies

Education

Bachelor’s or Master’s Degree in Engineering

Tools

Simulator

Synthesis tools

Job description

1 week ago Be among the first 25 applicants

• Typically requires minimum of 5-15 years of experience in System Verilog, UVM.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.
• If you thrive in a collaborative environment (even while social distancing) and enjoy learning new techniques and approaches for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you. Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• You will develop testbench components and stimulus using System Verilog UVM libraries. On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets. You will collaborate via design reviews and code reviews.

Required Technical And Professional Expertise:

• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design, Information Technology, and Engineering

• Industries

  Semiconductor Manufacturing

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