Senior/Staff Design Verification Engineer

Arteris; Austin (TX); On-site; USD 150,000 - 200,000; Full time

Job summary

A leading provider, Arteris, is seeking a Senior/Staff Design Verification Engineer to join their dynamic team in Austin, Texas. In this role, you will contribute to groundbreaking interconnect and memory hierarchy solutions needed for advanced SoC designs. Ideal candidates possess a master's degree, extensive verification experience, and a strong foundation in RTL and UVM methodologies. This is an excellent opportunity to work in a fast-paced, innovative environment alongside industry experts, impacting technology that powers smartphones, drones, and more.

Qualifications

• 5+ years of design and verification experience.
• Proficiency in scripting languages like Python.
• Strong skills in RTL (Verilog) and UVM/C test bench debugging.

Responsibilities

• Advanced UVM based test bench development and debugging.
• Defining and executing RTL verification test/coverage.
• Debugging RTL designs in Verilog and System Verilog.

Skills

RTL Verification

UVM expertise

Debugging

Scripting

Education

MS degree in EE, CS, or equivalent

BS degree

Job description

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Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

As a Senior/Staff Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs.

You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.

You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Key Responsibilities:

• Advanced UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at system level
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure
  
  

Experience Requirements / Qualifications:

• 5 or more years of design and verification experience and a plus in interconnect verification experience
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor provided VIPs for unit and system level verification
• Experience with Arm AMBA protocols
• This opportunity involves high performance, low power designs on a highly visible project
  
  

Education Requirements:

• MS degree in EE, CS, or equivalent preferred. BS degree minimum.
  
  

Estimated Annual Base Salary:

• $150,000 to $200,000 annually
  
  

About Arteris:

Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Computer Hardware Manufacturing, Software Development, and Semiconductor Manufacturing

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