Design Verification Engineer

AECOM; Austin (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

A leading company is seeking a Design Verification Engineer in Austin, Texas. This role requires understanding SOC architecture and developing verification plans while collaborating with design, architecture, and external teams to ensure successful SOC design verification. Candidates should possess a Master’s degree and experience with key hardware description languages.

Qualifications

• Master’s degree or equivalent in Electrical/Computer Engineering.
• Experience with Hardware Description Languages (Verilog, VHDL, SystemVerilog).
• Knowledge of digital design, circuit design, and computer architecture.

Responsibilities

• Develop and refine verification plans based on specifications.
• Create IP and subsystem verification plans, test benches, and sequences.
• Collaborate with cross-functional teams to ensure efficient verification.

Skills

Hardware Description Languages

Verification

Scripting Languages

Digital Design

Microprocessor Architecture

Education

Master’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Linux

Verilog

VHDL

SystemVerilog

Perl

Tcl

Python

Job description

Design Verification Engineer

Location: Austin, Texas, United States

Department: Hardware

Summary

Apple is seeking a Design Verification Engineer to join our team in Austin, Texas. The role involves understanding high-efficiency SOC architecture, standard SOC peripherals (SPI, I2C, UART, Timer, DMA), memory management schemes, low power specifications, multi-processor systems, DDR, PCIe, USB, PLL, power-up, and secure boot schemes. Responsibilities include creating coverage-driven verification plans from specifications, developing IP level modules and sub-system verification plans, and architecting UVM-based reusable test benches. The engineer will work closely with design, architecture, software, firmware, and external IP teams to verify the SOC design efficiently.

Responsibilities

• Develop and refine verification plans based on specifications.
• Create IP and subsystem verification plans, test benches, sequences, and infrastructure.
• Architect and implement UVM-based test benches and integrate VIPs to achieve targeted coverage.
• Collaborate with cross-functional teams to ensure efficient verification processes.

Minimum Qualifications

• Master’s degree or equivalent in Electrical Engineering, Computer Engineering, or related field.
• Experience with Hardware Description Languages (Verilog, VHDL) and SystemVerilog.
• Knowledge of digital design, circuit design, and computer architecture.
• Understanding of microprocessor architecture and assembly programming.
• Proficiency in scripting languages such as Perl, Tcl, or Python.
• Familiarity with Linux or Unix operating systems.
• Knowledge of semiconductor physics and transistor behavior.

Preferred Qualifications

N/A

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