Design for Test Engineer

Arrow Electronics, Inc.; San Jose (CA); On-site; USD 112,000 - 171,000; Full time

Benefits offered by this job

Medical insurance

Dental and vision insurance

401(k) with matching

Job summary

Arrow Electronics, Inc. in San Jose, CA seeks an experienced DFT Design Engineer to lead scan insertion, ATPG, MBIST and JTAG activities for 3nm and 5nm networking IPs. You will generate patterns, run timing-aware simulations, and debug with Verdi across SoCs. Strong scripting in Perl/Shell/TCL is required.

The role offers full-time on-site employment with competitive compensation and comprehensive benefits in a dynamic, global semiconductor services company.

Qualifications

• 5 to 7 years of experience in design for test engineering.
• Hands-on expertise in scan insertion, ATPG, GLS, and pattern simulation with and without timing.
• Experience with MBIST insertion and verification.
• Experience with IEEE 1149.1 JTAG insertion and validation.
• Scripting skills in Perl, Shell, and TCL.
• Experience on multi-million-gate SoCs in networking or related IPs such as PLL and SerDes is preferred.
• Familiarity with Mentor Tessent toolset.
• B.Tech or M.Tech in Microelectronics or Electronics.
• Strong communication skills.
• Knowledge of low-power DFT is valued.

Responsibilities

• Implement DFT for 3nm and 5nm networking chips, including IP-level DFT work.
• Perform RTL checks for scan-insertion readiness using Synopsys Spyglass.
• Carry out scan insertion with Tessent TestKompress.
• Generate ATPG patterns in compressed and uncompressed modes using Mentor Tessent, Cadence Modus, and Synopsys Tetramax.
• Run pattern simulations across multiple corners using VCS.
• Debug mismatches with Verdi.
• Write scripts in Perl, Shell, and TCL to support automation and flow improvements.
• Enhance DFT flows through DAeRT automation initiatives.
• Improve Makefiles with extended scripts and targets to streamline the flow.
• Perform MBIST insertion and verification at block and top levels.
• Support silicon debug and bring-up for both block and top levels.
• Insert and verify IEEE 1149.1 JTAG functionality.

Skills

ATPG

Scan insertion

GLS

Pattern simulation

MBIST insertion

IEEE 1149.1 JTAG

Scripting: Perl

Scripting: Shell

Scripting: TCL

Mentor Tessent

SoC design experience

Strong communication

Low-power DFT

Education

B.Tech or M.Tech in Microelectronics or Electronics

Tools

Mentor Tessent

Cadence Modus

Synopsys Tetramax

VCS

Verdi

Job description

Salary: $112,200 - 170,500 per year

Requirements

• We look for 5 to 7 years of experience in design for test engineering.
• We need hands-on expertise in scan insertion, ATPG, GLS, and pattern simulation with and without timing.
• We expect experience with MBIST insertion and verification.
• We require experience with IEEE 1149.1 JTAG insertion and validation.
• We value scripting skills in Perl, Shell, and TCL.
• We prefer experience working on multi-million-gate SoCs in networking, consumer, or related IPs such as PLL and SerDes.
• We use Mentor Tessent and look for familiarity with this toolset.
• We seek candidates with a B.Tech or M.Tech in Microelectronics or Electronics.
• We need strong communication skills.
• We value knowledge of low-power DFT.

Responsibilities

• We implement DFT for 3nm and 5nm networking chips, including IP-level DFT work.
• We perform RTL checks for scan-insertion readiness using Synopsys Spyglass.
• We carry out scan insertion with Tessent TestKompress.
• We generate ATPG patterns in compressed and uncompressed modes using tools such as Mentor Tessent, Cadence Modus, and Synopsys Tetramax.
• We run pattern simulations both with and without timing across multiple corners using VCS.
• We debug mismatches with Verdi.
• We write scripts in Perl, Shell, and TCL to support automation and flow improvements.
• We enhance DFT flows through DAeRT automation initiatives.
• We improve Makefiles with extended scripts and targets to streamline the flow.
• We perform MBIST insertion and verification at block and top levels.
• We support silicon debug and bring-up for both block and top levels.
• We insert and verify IEEE 1149.1 JTAG functionality.

Technologies

• Flow
• Support
• Perl
• Cloud

More

We are Arrow, through our eInfochips team, a leading global provider of product engineering and semiconductor design services with more than two decades of experience, over 500 products developed, and 40 million deployments across 140 countries. We partner with major technology companies and support connected product innovation for global clients. This is a full-time, fully on-site role in San Jose, California, with an annual hiring range of $112,200 to $170,500. We offer competitive compensation and a strong benefits package that includes medical, dental, and vision insurance, 401(k) with matching contributions, short- and long-term disability coverage, HSA/HRA options, paid time off, tuition reimbursement, and growth opportunities.

last updated 41 week of 2026