Design for Test Engineer

Apple Inc.; Cupertino (CA); Hybrid; USD 147,000 - 218,000; Full time

Benefits offered by this job

Stock-based compensation programs

Education reimbursement

Medical and dental coverage

Retirement benefits

Employee stock purchase plan

Excellent relocation support

Job summary

Apple Inc. in Cupertino, CA is seeking a DFT/RTL engineer to design and implement DFT architectures for complex chips. The role collaborates with design and verification teams, runs STA checks, and develops ATPG test vectors to improve yield.

You will engage with test engineers to bring up vectors on silicon and work on power reduction strategies. Qualifications include a Master’s in a related field and strong Verilog, DFT, ATPG, and scripting experience.

Qualifications

• Master’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, or related field with 2 years of related experience.
• Experience designing and verifying RTL using Verilog.
• Knowledge of MBIST, march algorithms and memory fault models.
• Experience designing JTAG architecture and DFT control registers.
• Automation of DFT design flows using Python or Perl.
• Knowledge of STA for timing analysis and RTL/gate-level simulations.

Responsibilities

• Develop and document DFT architecture and specifications.
• Implement DFT infrastructure and RTL Verilog for DFT logic.
• Collaborate with designers to integrate DFT and run checks.
• Coordinate with DV team to verify RTL and gate-level designs.
• Generate ATPG vectors and analyze test coverage across fault models.
• Engage with test engineers to bring up vectors on silicon.
• Support TTR and silicon diagnosis efforts.
• Handle schedules and multi-functional engineering tasks.
• Apply low-power techniques to reduce chip power consumption.

Skills

RTL design & verification

Verilog

Python/Perl scripting

JTAG/DFT control

STA timing analysis

ATPG & test vectors

Silicon failure analysis

Low-power design

Education

Master’s degree in Computer/Electrical/Electronics Engineering

Tools

VCS

NCSIM

Job description

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop and implement DFT (Design For Test) architecture and document DFT specifications. Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic. Collaborate with designers to integrate DFT implementations and run various checks. Partner with designers on STA (Static Timing Analysis), physical, power and logical issues. Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders). Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage. Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time Reduction) and silicon diagnosis efforts. Handle schedules and support multi-functional engineering efforts. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $146,717 - $218,000/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Experience and/or education must include:
• Designing and verifying RTL using Verilog hardware description language.
• Knowledge of MBIST, march algorithms and memory fault models.
• Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing
• Automating DFT design flows using Python or Perl scripting languages
• Knowledge of STA for timing analysis.
• Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues
• Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models
• Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes
• Applying low-power design techniques to reduce overall chip power consumption

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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