Design Engineering Architect - Systems and Interfaces

Cadence; San Jose (CA); On-site; USD 186,000 - 345,000; Full time

Benefits offered by this job

Paid vacation

Paid holidays

401(k) plan with employer match

Employee stock purchase plan

Medical/dental/vision plans

Job summary

Cadence in San Jose seeks a Design Engineering Architect to lead integration of complex Cadence IP in SoCs. You will guide pre-/post-sales engagements, develop reference designs, and create technical content for field teams.

The role drives advanced IP integration, collaborates across sales, marketing, and engineering, and requires deep RTL and system architecture expertise. Occasional travel applies, with strong compensation and benefits.

Qualifications

• Experience with high-speed interface protocols (PCIe, UCIe, Ethernet).
• Expertise in integrating IP into complex SoCs and on-chip interconnects.
• Proficient in RTL writing and debugging (Verilog, SystemVerilog).
• Strong design, verification, and post-silicon support capabilities.

Responsibilities

• Serve as the technical authority for Cadence interface controllers and system-level IP integration in customer engagements.
• Lead resolution of critical customer issues and escalations with cross-functional teams.
• Develop reference designs, technical collateral, and application notes for IP integration.
• Develop and deliver training for customers and field engineers.
• Provide advanced technical guidance on IP integration and system deployment.
• Lead product evaluations and release-readiness reviews.
• Analyze customer needs to propose product and documentation improvements.

Skills

RTL design

PCIe

UCIe

Ethernet

AMBA protocols

Verilog

SystemVerilog

SoC integration

Synthesis flows

Education

BS in EE/CS with 12+ years

MS in EE/CS with 8+ years

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Architect - Systems and Interfaces

San Jose

Job Description

The SSG Central Applications Engineering team seeks an experienced SoC design engineer to enable the integration and deployment of Cadence IP in complex customer system designs. As a Design Engineering Architect, you will serve as a senior technical leader, enabling the successful integration and adoption of Cadence interface IP in our customers' SoCs.

In this role, you will work closely with the SSG IP sales, marketing, development engineering, and customer support teams. You will contribute to product definition, develop technical content and examples, and drive complex pre-sales and post-sales engagements.

The Cadence Silicon Solutions Group (SSG) develops and licenses IP for SoC and ASIC designs, including high-performance DSPs, CPUs, interface IP, DDR controllers, hardware accelerators, and subsystems. These technologies enable applications such as machine learning, edge AI, radar, audio, speech, and vision. Leading semiconductor companies use Cadence IP in billions of chips shipped annually. This role enables customer adoption of Cadence IP and addresses complex system integration challenges.

Responsibilities

• Serve as the technical authority for Cadence interface controllers and system-level IP integration in customer engagements.
• Lead resolution of critical customer issues and escalations, coordinating with development engineering, sales, marketing, and customer support teams on pre-sales and post-sales engagements.
• Develop reference designs, technical collateral, and application notes for IP integration, SoC design, and verification.
• Develop and deliver training for customers and field application engineers.
• Provide advanced technical guidance to customers, support teams, and field application engineers on IP integration, configuration, and system-level deployment.
• Lead product evaluations and release-readiness reviews, identifying integration risks, usability gaps, and advanced customer use cases.
• Analyze and propose enhancements to our products and documentation based on customer needs and use cases.

Required Skills

• Demonstrated expertise in the RTL design, verification, and debug of high-speed interface protocols such as PCIe, UCIe, and Ethernet.
• Experience integrating IP into complex SoCs, with a strong understanding of system architecture, interfaces, and on-chip interconnects.
• Experience with AMBA protocols, including ACE, CHI, AXI, and APB.- Proficient in writing and debugging RTL (Verilog, SystemVerilog).
• Experience with end-to-end SoC implementation flows, including RTL synthesis, design constraints, DFT, CDC, and static timing analysis.
• Demonstrated ability to analyze complex hardware and system problems, identify root causes, and drive cross-functional teams to resolution.
• Strong written and verbal communication skills.
• A BS in EE/CS with 12+ years, or an MS in EE/CS with 8+ years of relevant work experience.
• Ability to travel up to 10% of the time, including internationally.

The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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