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Cadence Design Systems seeks a layout engineer to produce high-quality analog/mixed-signal layouts and IP blocks. You will participate in the back-end flow from floor planning to verification, collaborating with circuit designers and teams worldwide to meet tight schedules.
As part of the Cadence IP Group custom layout team, you will work with Virtuoso and related tools to achieve high speed, accuracy and conformance to design rules across multiple process nodes.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team of layout designers creating challenging IP designs for the consumer, industrial, and automotive markets. Our designs are fabricated in the world’s leading edge silicon processes for companies ranging from large multinational companies to hot start-ups. Learn on-the-job how to apply your engineering background to create these robust high performance analog designs. Working with experienced skilled designers, you will be part of the design team using Cadence design tools.
We are looking for a layout engineer capable of producing quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers. Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules. The Cadence IP Group custom layout team develops and delivers a variety of high-quality high speed and high accuracy CMOS integrated circuits IP for several foundries and process nodes down to 5n and even below. We are deeply involved in finfet layout and even beyond (gate all-around). As part of Cadence, the Cadence IP group custom layout team not only has access to all the current and future Cadence layout and verification tools, we also participate in the development and validation of the Cadence Virtuoso software, which the most used in the industry.
As a custom layout designer, you will be involved in: Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency Working with custom layout designers from groups all over the world to build high quality IP and test-chips Working with circuit designers from groups all over the world to understand their technical and schedule needs Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools BSEE, MSEE Exposure to microelectronics design and requirements Understanding of layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques like matching, shielding etc., Exposure to Cadence Virtuoso Layout and physical verification tools Team player, driven, self-motivated and autonomous Excellent communication, presentation and customer service skills
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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.