CPU Verification Engineer

Apple Inc.; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Austin, TX is seeking an experienced CPU Implementation Engineer to drive block-level design and backend flows for silicon products.

You will work with micro-architects to refine microarchitecture, optimize PPA, and ensure RTL-to-GDS convergence using standard CAD tools. Responsibilities include collaborating with cross-functional teams on floorplanning, timing, power, reliability, and testability, and coordinating memory macros with IP teams to improve silicon yield and

Qualifications

• BS EE/CE or equivalent experience.
• Strong communication and teamwork skills.
• Willingness to address diverse design challenges.

Responsibilities

• Define micro-architecture and perform PPA trade-offs.
• Drive RTL-to-GDS design convergence with CAD tools.
• Deliver block-level design and ensure backend flow closure.
• Collaborate on CPU floorplanning, timing, power, reliability, and testability with cross-functional teams.

Skills

Communication skills

Teamwork

Education

BS EE/CE or equivalent experience

Tools

RTL/ASIC design tooling

Scripting/Programming basics

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

As a CPU Implementation Engineer you will drive or participate in the following - Will work extensively with micro-architects to define the micro-architecture, perform design feasibility and do power, performance, and area (PPA) trade-offs - Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA - Will be responsible for block-level design delivery along with closure of backend flows, electrical requirements and improving silicon yield - Will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design - Will work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability - Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA

Minimum Qualifications

• - BS EE/CE or equivalent experience.
• - Be an outstanding teammate with excellent communication skills and the desire to address diverse challenges.

Preferred Qualifications

• Solid electrical engineering fundamentals in logic design and digital circuits
• Basic knowledge of CPU pipeline, and physical design concepts related to timing and power
• Basic knowledge of scripting/programming acquired during coursework, internship or industry work
• Ability to work well in a team, self-motivated and excellent communication skills

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.