CPU Implementation Engineer

Apple Inc.; Beaverton (OR); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading technology company in Beaverton is seeking a CPU Implementation Engineer to drive design convergence and deliver block-level design. Candidates should have a Bachelor's degree and over 10 years of experience in logic design and digital circuits, with proficiency in tools like TCL and Perl. Join a passionate team to contribute to groundbreaking products and technologies.

Qualifications

• Minimum 10+ years of relevant industry experience.
• Experience with high-performance CPU architecture.
• Familiarity with physical design partitioning and timing budgeting.

Responsibilities

• Drive RTL-to-GDS design convergence through optimizations.
• Responsible for block-level design delivery.
• Work with cross-functional teams on power and reliability aspects.

Skills

Logic design

Digital circuits

Low power design techniques

High frequency design techniques

TCL

Perl

Education

Bachelor's degree in relevant field

Tools

Synthesis tools

Place-and-route tools

STA tools

Power analysis tools

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

Description

As a CPU Implementation Engineer, you will drive or participate in the following:• Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs• Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA• Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield• Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design• Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability• Work closely with custom IP teams define and co-optimize memory macros, library standard cells to improve design PPA

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience in logic design and digital circuits
• Experience with low power and high frequency design techniques
• Experience with TCL or Perl

Preferred Qualifications

• Familiarity with high performance CPU microprocessor architecture and memory sub-system
• Knowledge in deep sub-micon technology along with its implications to timing, power, and area
• Must have proficiency in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with floor-planning, physical design partitioning, and timing budgeting, to converge complex designs
• Excellent communication and interpersonal skills
• Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple accepts applications to this posting on an ongoing basis.