Physical Design Engineer- Staff to Sr. Staff

QUALCOMM, Inc.; Austin (TX); On-site; USD 174,000 - 262,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a senior Clock Physical Design Engineer in Austin, TX. You will own clock PD methodology, implement advanced clock structures, and drive signoff across NSP ASIC/SoC designs.

The role requires 10+ years in ASIC/SoC physical design with hands-on experience in clock distribution, SPICE analysis, and multi-tool signoff. Collaboration across PD, timing, power, PLL, and CAD teams is essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC Physical Design with clock implementation and timing closure.
• Proven experience taking complex designs through physical design convergence and tapeout.

Responsibilities

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures (H-trees, mesh, spine, hierarchical distribution).
• Perform detailed SPICE simulation and transistor-level analysis of clock structures for waveform quality and robustness.
• Analyze clock-related timing, power, noise, and variation across operating conditions.
• Drive clock convergence and signoff across modes, corners, voltages, temperatures, and frequencies.
• Collaborate with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams on clock signoff.

Skills

Clock architecture

Timing closure

Power-aware design

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or related

Master's degree in Science/Engineering or related

PhD in Science/Engineering or related

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

Synopsys PrimeTime

RC extraction tools

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

QCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design Engineer to develop, optimize, and sign off advanced clocking solutions for next-generation NSP designs. The ideal candidate will have 10+ years of ASIC/SoC physical design experience, with deep expertise in high-performance clock architecture and implementation, including clock H-trees, clock mesh, and clock spine methodologies.

This role requires strong understanding of the complete clock path, from clock source and distribution architecture through block-level implementation and signoff. The engineer will work across physical design, timing, power, PLL, and CAD teams to optimize clock performance, power, variation, noise, and robustness across advanced technology nodes.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Key Responsibilities

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures, including:
  • Clock H-trees, Clock mesh architectures, Clock spine methodologies, Hierarchical clock distribution across block and top-level designs, Clock gating and low-power clock distribution techniques
• Perform detailed SPICE simulation and transistor-level analysis of critical clock structures to understand clock waveform quality, delay, slew, sensitivity, and robustness across operating conditions.
• Analyze and debug clock-related:
  • Timing and clock skew, Dynamic and leakage power, Signal integrity and noise, On-chip variation, Jitter and clock uncertainty, Duty-cycle distortion, Slew and waveform degradation, Physical implementation and routing issues
• Drive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.
• Analyze clock distribution tradeoffs across performance, power, area, skew, insertion delay, variation, and robustness, and recommend appropriate clock architectures and implementation strategies.
• Provide technical feedback and guidance to block-level and top-level Physical Design engineers on:
  • Required clocking fixes, Clock tree/mesh/spine optimization opportunities, Clock routing and physical implementation issues, Timing and variation concerns, Power reduction opportunities, Potential signoff risks
• Collaborate closely with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams to align:
  • Clock source assumptions, PLL and clock-source characteristics, Jitter budgets, Clock uncertainty, Clock latency and skew targets, Variation assumptions, MMMC constraints, Clock signoff methodology
• Perform detailed clock timing analysis using Synopsys PrimeTime and correlate implementation, STA, extraction, and SPICE results where required.
• Work with implementation teams to develop and tune customized clock implementation recipes and methodologies for aggressive performance and power targets.
• Support clock-related ECO development and implementation during timing closure and tapeout convergence.
• Evaluate clock networks for IR-drop, EM, crosstalk, signal integrity, and reliability risks, and work with implementation and power-integrity teams to resolve issues before tapeout.
• Drive clock-related tapeout readiness and ensure all clock structures meet required timing, power, physical verification, and reliability signoff criteria.
• Develop and enhance clock analysis, debug, characterization, and implementation automation using TCL, Python, Perl, and Linux shell scripting.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC Physical Design, with significant hands‑on experience in high-performance clock implementation and timing closure.
• Proven experience taking complex ASIC/SoC designs through physical design convergence and successful tapeout.
• Deep hands‑on expertise with advanced clock distribution methodologies, including:
  • Clock H-trees
  • Clock mesh
  • Clock spines
  • Hierarchical clock distribution
  • Clock gating and low-power clock implementation
• Strong understanding of:
  • Clock skew and insertion delay
  • Jitter and clock uncertainty
  • Slew and duty‑cycle distortion
  • PVT and on‑chip variation
  • Clock power optimization
  • Clock signal integrity
  • Clock‑related IR/EM concerns
  • Multi‑mode/multi‑corner timing analysis
• Hands‑on experience with SPICE simulation and the ability to analyze clock circuits and distribution structures at the transistor and waveform level.
• Strong experience with industry‑standard Physical Design and signoff tools, including:
  • Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus
  • Synopsys PrimeTime
  • RC extraction and signal‑integrity analysis tools
  • Physical verification and DRC/LVS signoff flows
• Strong understanding of advanced‑node timing, parasitics, variation, power integrity, and reliability effects on clock distribution.
• Proficiency in TCL, Python, Perl, and Linux/Unix environments.

Preferred Skills

• Experience developing and deploying custom clock methodologies for high-frequency designs rather than relying exclusively on conventional CTS approaches.
• Experience with advanced technology nodes and clock‑design challenges associated with increased process variation, interconnect resistance, power density, and reduced voltage margins.
• Strong understanding of PLL behavior, jitter, clock‑source modeling, and clock uncertainty budgeting.
• Experience correlating SPICE, STA, extraction, and physical implementation results to identify root causes of clock performance or signoff issues. Familiarity with Infinisim or PrimeClock a plus.
• Knowledge of dynamic power, IR-drop, electromigration, signal integrity, crosstalk, and reliability analysis as they relate specifically to high‑performance clock networks.
• Experience working across hierarchical SoC implementation, including interaction between clock source, top‑level clock distribution, and block‑level clock networks.
• Ability to influence implementation methodology and provide clear technical guidance to block owners, top‑level PD engineers, timing teams, and CAD teams.
• Strong analytical and debugging skills with the ability to drive complex clocking problems from initial characterization through root cause and final signoff.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$174,400.00 - $261,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.