CPU RTL Engineer - High-Performance, Low-Power CPU

MaC VC; Austin (TX); On-site; USD 176,000 - 263,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking engineers for CPU RTL development aimed at high-performance, low-power devices. You will collaborate with chip architects to define micro-architecture and participate early in the product life cycle.

Responsibilities include RTL ownership, architecture exploration, and cross-functional verification and design delivery to meet timing and power goals. A strong background in Verilog/VHDL and power-aware design is required.

Qualifications

• MS degree in Computer or Electrical Engineering with 5+ years CPU RTL experience.
• Thorough knowledge of microprocessor architecture; RAS/PMU and power management.
• Verilog and/or VHDL knowledge with simulators and waveform debugging tools.
• Strong logic design principles with timing and power awareness.

Responsibilities

• Performance exploration with CPU modeling team.
• Microarchitecture development and specification from high-level exploration to detailed specs.
• RTL ownership: development, assessment and refinement to power, performance, area and timing goals.
• Functional verification support for the design verification team.
• Performance verification support to ensure RTL meets performance goals.
• Design delivery with multi-functional teams, focusing on timing, area, reliability, and power.
• Collaborate with Software, Firmware and platform teams to enable CPU system features.

Skills

CPU RTL experience

Microprocessor architecture

Verilog/VHDL

Simulation tools

Power management

Active/Idle power

Clock architecture

Debug/Trace architecture

Low power microarchitecture

High-performance CPU

Perl/Python scripting

Education

MS in Computer or Electrical Engineering

Job description

Qualcomm Technologies, Inc. is seeking engineers for CPU RTL development aimed at high-performance, low-power devices. You will collaborate with chip architects to define micro-architecture and participate early in the product life cycle.

Responsibilities include RTL ownership, architecture exploration, and cross-functional verification and design delivery to meet timing and power goals. A strong background in Verilog/VHDL and power-aware design is required.