CPU RTL Design Engineer — Hybrid

Intel Corporation; Austin (TX); Hybrid; USD 91,000 - 173,000; Full time

Benefits offered by this job

14 paid holidays per calendar year

3 weeks of paid vacation

4-week paid sabbatical every four

Employee stock purchase program

Performance bonuses

Job summary

Intel Corporation in Texas, Austin seeks an RTL Design Engineer to develop RTL for CPU components and participate in architecture decisions that optimize performance, power, and area. You will ensure verification readiness and work with a cross-functional team to deliver high-quality CPU designs.

Collaborating with verification teams, you will address RTL test failures, document microarchitectural specs, and support SoC customers with CPU block integration to enable broad system use.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related STEM field.
• 3+ months of CPU logic design, computer architecture and RTL coding experience.
• Experience with Verilog/SystemVerilog or VHDL.

Responsibilities

• Develop RTL coding for CPU components and CPU IP blocks.
• Contribute to architecture and microarchitecture features to improve performance, power and area.
• Write RTL and verify against timing goals, ensuring design readiness for physical implementation.
• Review verification plans and tests; resolve RTL test failures.
• Document microarchitectural specifications and support SoC integration.

Skills

CPU Logic Design

Computer Architecture

Digital design

RTL coding

Verilog/SystemVerilog/VHDL

Scripting (Python/Perl/TCL)

Education

Bachelor's degree in Electrical or Computer Engineering

Master's or PhD (preferred)

Tools

RTL design tools

Job description

Intel Corporation in Texas, Austin seeks an RTL Design Engineer to develop RTL for CPU components and participate in architecture decisions that optimize performance, power, and area. You will ensure verification readiness and work with a cross-functional team to deliver high-quality CPU designs.

Collaborating with verification teams, you will address RTL test failures, document microarchitectural specs, and support SoC customers with CPU block integration to enable broad system use.