CPU Physical Electrical Analysis Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

Apple Inc. is looking for a CPU Physical Electrical Analysis Engineer in Beaverton, Oregon. This role requires deep knowledge in block-level implementation and a minimum of 10 years of experience in silicon level power delivery and electromigration analysis. You will play a key role in driving design convergence across multiple blocks and teams, ensuring effective communication and timely project delivery.

The ideal candidate should possess scripting skills for SAPR or EMIR flow automation and experience with industry-standard tools like Apache Redhawk and Cadence Voltus. Join us to contribute to Apple's innovation!

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with silicon level power delivery, electromigration, and IR drop analysis.
• Experience with scripting of SAPR or EMIR flow automation.

Responsibilities

• Drive block and top-level EMIR/electrical verification closure.
• Work on power grid design and implementation.
• Collaborate with multi-functional teams for design and sign-off.

Skills

Power delivery analysis

Electromigration & IR drop analysis

Scripting for flow automation

Communication & presentation skills

Education

Bachelor's degree

Tools

Apache Redhawk

Cadence Voltus

Job description

CPU Physical Electrical Analysis Engineer

Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

• Drive block and top-level EMIR/electrical verification closure
• Work on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environment
• Work multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results, with methodology teams to cover unique use cases, with implementation teams to drive design and sign-off closure, and with the SOC level teams to meet IP delivery quality and schedule

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with silicon level power delivery, electromigration, and IR drop analysis
• Experience with scripting of SAPR or EMIR flow automation for the efficient processing of large scale design and analysis data, debugging of issues, and isolating design sensitivities

Preferred Qualifications

• Experience implementing high-performance and low-power VLSI designs
• Experience with SAPR/PNR design flow infrastructure
• Understanding of challenges related to latest deep sub-micron technology
• Produce impactful design fixes and automate wherever possible, spanning multiple tool domains in physical construction and analysis
• Working knowledge of industry standard tools like Apache Redhawk and Cadence Voltus as well as PNR implementation, layout tools, verification, and STA
• Strong communication and presentation skills to regularly summarize the state of the design and drive design convergence across multiple blocks and teams in a timely fashion

Equal Employment Opportunity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.