CPU Implementation Engineer

Apple Inc.; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company as a CPU Implementation Engineer, where you'll be at the forefront of designing high-performance microprocessors. In this role, you'll be responsible for all phases of physical design implementation, from RTL to GDSII delivery. Your expertise in RTL synthesis, static timing analysis, and power analysis will be crucial as you collaborate with a diverse team of engineers to innovate and optimize cutting-edge technologies. This opportunity offers a dynamic work environment where your contributions will directly impact the future of technology and the products that enhance people's lives.

Qualifications

• Master’s degree or equivalent in Computer or Electrical Engineering.
• Experience in RTL synthesis and static timing analysis.

Responsibilities

• Responsible for physical design implementation for microprocessors.
• Collaborate with multi-functional teams for design validation.

Skills

RTL Synthesis

Floor planning

Place and Route

Static Timing Analysis

Logical Equivalency Check

Power Analysis

Scripting (Python, Tcl, Perl)

Hardware coding (Verilog)

Education

Master’s degree in Computer Engineering

Master’s degree in Electrical Engineering

Job description

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Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Responsible for all phases of physical design implementation for high efficiency and high performance microprocessor from register transfer language (RTL) to final GDSII delivery. Perform front end implementation tasks such as feature feasibility study, synthesis, Static timing analysis (STA) and Power analysis. Work extensively with Micro-architects to define memory subsystem, perform feasibility, make area, frequency, performance, power trade-offs and design & balance the pipeline stages. Drive RTL-to-GDS flow through synthesis and place-and-route targeting ambitious targets for power, performance, and area. Generate and Implement Embedded Configurable Operating System (ECOs) to close the design. Collaborate with Computer-aided design (CAD) and Methodology team to develop physical design methodologies. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.40 hours/week.

Minimum Qualifications

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.
• Experience and/or education must include:
• RTL Synthesis
• Floor planning, Place and Route
• Static Timing Analysis
• Logical Equivalency Check
• Power Analysis
• Scripting: Python, Tcl or Perl
• Hardware coding: Verilog

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

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