CPU Custom Library Cell Design (IC)

Nuvacore; Austin (TX); On-site; USD 140,000 - 250,000; Full time

Job summary

Nuvacore is assembling a Custom Library Circuit Engineer to drive library cell design and PPA optimization for next-gen CPU workloads. You will own end-to-end IP closure, from schematic to layout through DRC/LVS and parasitic extraction, while partnering with foundry and CAD teams to optimize cells for performance and power.

Ideal candidates have 12+ years in standard cell or memory design, strong transistor-level experience, and proficiency with EDA tools.

Qualifications

• BS or MS in Electrical Engineering or related field.
• 12+ years of experience in standard cell and/or custom memory circuit design.
• Hands-on transistor-level design experience with static circuits and latches/flops.
• Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization.
• Experience providing feedback to foundry partners to improve PPA/yield.

Responsibilities

• Design and characterize library cells to optimize PPA at advanced nodes.
• Own end-to-end library IP closure from schematic to characterization.
• Collaborate with Foundry/PDK, CAD, Physical Design, and DFT teams on process technology.
• Define tools, flows, and methodology to raise design efficiency.

Skills

Standard cell design

Custom memory design

Transistor-level design

EDA tools proficiency

PPA optimization

Team collaboration

Education

BS or MS in Electrical Engineering

Tools

Schematic/Layout tools

DRC/LVS verification

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

As a Custom Library Circuit Engineer, you will participate in the following :

• Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and special purpose AOI cells to optimize PPA at advanced process nodes.

• Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization

• Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark new process technology, validate IP on test chips, and co-optimize cells for downstream design PPA.

• Define and drive adoption of Tools, Flows, and Methodology — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with (ideally) 12+ years of experience in standard cell and/or custom memory circuit design.

• Hands-on transistor-level design experience with static circuits and state-retaining elements (latches, flops), as well as custom logic gates at advanced CMOS nodes.

• Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom cell and memory design workflows.

• Experience providing feedback to foundry partners to help improve PPA, yield, and other important qualities in future revisions of the PDK.

• Well-versed in STA and Liberty/CCS model correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.

• Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.

REQUIREMENTS — PREFERRED

• Experience across the full design flow of a custom circuit — cell/memory architecture, circuit design, compiler automation, characterization, and timing/model generation.

• Experience translating PDK device characteristics into circuit decisions.

• Proven PPA-focused execution for standard cells, including architecture trade-offs, critical-path modeling, full-cut analysis, and Monte Carlo variation studies.

• Experience using Agentic AI tools for productivity and automation.

$140,000 - $250,000 a year