CPU Verification Engineer

Nuvacore; Austin (TX); On-site; USD 140,000 - 250,000; Full time

Job summary

Nuvacore in Austin is seeking Verification Engineers at multiple levels—from Senior Engineer to Principal—to prove the correctness of the Nuvacore CPU. You will build test plans, environments, and checkers to expose deep bugs long before silicon, collaborating with architecture and RTL.

Responsibilities include developing directed and random tests in assembly, C, and sequences, plus coverage monitors and performance verification to align RTL with models, while partnering with teams across FPGA,

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
• Strong knowledge of CPU micro-architecture and digital logic — pipelines, out-of-order execution, and branch prediction.
• Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests in assembly for CPU verification.

Responsibilities

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise the pipeline end to end.
• Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
• Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Skills

CPU verification

Testbenches & checks

C/C++

SystemVerilog

Python scripting

Test plans

Coverage

Education

Bachelor's degree in ECE/CS

Tools

Python

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore CPU. As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.

• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise the pipeline end to end.

• Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.

• Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.

• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.

• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS — MUST HAVE

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.

• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.

• Strong knowledge of CPU micro-architecture and digital logic — pipelines, out-of-order execution, and branch prediction.

• Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.

• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).

• Experience writing and debugging tests in assembly for CPU verification.

REQUIREMENTS — NICE TO HAVE

• Experience on one or more of Front-end / execution-unit verification, load/store cache verification, SoC/System verification, Debug/Power mgmt verification.

• Random instruction sequence (RIS) stimulus generation.

• Constrained-random verification and coverage-driven closure.

• Assertions and formal verification.

• Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

• Driving a verification problem end-to-end to sign-off.

$140,000 - $250,000 a year