CPU Architecture Verification Engineer - RIS & Golden

NUVACORE; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Nuvacore is building a high-performance, low-power CPU and seeks Verification Engineers at multiple levels to validate architectural correctness. You will drive verification strategy, build robust environments, create RIS stimuli, and collaborate with architects and RTL teams for end-to-end verification.

Roles span Senior to Principal levels, focusing on architectural state vs. specification, coverage closure, and bringing up verification flows across emulation, FPGA, and silicon stages.

Qualifications

• Degree in Electrical/Computer Engineering, CS, or equivalent.
• 4+ years design-verification (Senior) or 15+ years (Principal) on CPU or complex digital design.
• Strong CPU architecture knowledge, ISA familiarity (x86, ARM, or RISC-V).
• Hands-on verification: test plans, testbenches, checkers, coverage.
• Proficiency in C/C++/Rust and/or SystemVerilog; Python or Perl.
• Experience writing and debugging tests in assembly for CPU verification.

Responsibilities

• Plan & Strategy: define verification scope and strategy for architectural correctness.
• Environment Setup: build and maintain verification environments and co-simulation with golden model.
• Test & Debug: generate assembly and RIS stimuli for CPU verification.
• Coverage Closure: define coverage space and monitors; assess completion.
• Cross-functional Collaboration: work with architects and RTL to fix mismatches and support bring-up.

Skills

C/C++/Rust

SystemVerilog

Python

Assembly

Education

Electrical/Computer Engineering, CS degree or equivalent

Tools

Python

Perl

Co-simulation

Job description

Nuvacore is building a high-performance, low-power CPU and seeks Verification Engineers at multiple levels to validate architectural correctness. You will drive verification strategy, build robust environments, create RIS stimuli, and collaborate with architects and RTL teams for end-to-end verification.

Roles span Senior to Principal levels, focusing on architectural state vs. specification, coverage closure, and bringing up verification flows across emulation, FPGA, and silicon stages.