Senior/Principal CPU Architecture Verification Engineer

NUVACORE, Inc.; Austin, Northern (TX, KY); Hybrid; USD 130,000 - 210,000; Full time

Job summary

Nuvacore, Inc. in Austin, TX is seeking Verification Engineers at multiple levels to help prove architectural correctness of the Nuvacore CPU. You will join the design verification team and drive verification across the architecture and golden model.

You will build stimuli, checkers, and flows, collaborate with architecture and RTL, and support emulation, FPGA, and silicon bring-up across seniority levels.

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience on CPU or complex digital design.
• Strong knowledge of CPU architecture and micro-architecture with ISA knowledge (x86/ARM/RISC-V).
• Hands-on functional verification: test plans, testbenches, checkers, and coverage.
• Proficiency in C/C++/Rust and/or SystemVerilog, plus Python.
• Experience writing and debugging tests in assembly for CPU verification.

Responsibilities

• Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness.
• Environment Setup: Build and scale verification environments, co-simulation against a golden model.
• Test & Debug: Generate stimulus in assembly and RIS to exercise the ISA and corner cases.
• Coverage Closure: Define coverage, write monitors, and analyze results.
• Cross-functional Collaboration: Partner with architects and RTL to root-cause mismatches and support bring-up.

Skills

CPU architecture

Micro-architecture

C/C++/Rust

SystemVerilog

Python scripting

Education

Bachelor's or higher in Electrical/Computer Engineering, CS

Job description

Nuvacore, Inc. in Austin, TX is seeking Verification Engineers at multiple levels to help prove architectural correctness of the Nuvacore CPU. You will join the design verification team and drive verification across the architecture and golden model.

You will build stimuli, checkers, and flows, collaborate with architecture and RTL, and support emulation, FPGA, and silicon bring-up across seniority levels.