CMP Process Engineer — Semiconductor Flatness & Yield

Samsung Electronics America; Taylor (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Life insurance & 401(k) matching

Onsite cafés & fitness facilities

Maternity & paternity leave

PTO + holidays

Wellness incentives

MBO bonuses

Job summary

Samsung Austin Semiconductor is seeking a CMP Process Engineer to own critical planarization steps in a high-volume fab. You will control removal rate, optimize recipes, and manage defects to ensure wafer flatness and yield.

Experience with CMP tools and metrology, plus DOE for process optimization, is required. Join a team that analyzes materials, implements process improvements, and collaborates across fabs.

Qualifications

• Basic requirement BS or MS in Chemical, Mechanical, Electrical, or Industrial Engineering, Physics, Chemistry, Material Science, or Computer Science.
• A minimum 5 years of related experience; Semiconductor Process Flows.
• Previous experience in a high-volume semiconductor manufacturing environment desired.
• Applicable manufacturing experience in other industries can be considered.
• Basic CMP Knowledge: Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.
• Prefer to have some level of Equipment Familiarities: Hands‑on experience with major industry CMP tools: AMAT/EBara and their end point systems.
• Data & Statistics: Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software like JMP or Spotfire.
• Problem Solving: Ability to drive root‑cause analysis using methodologies like FMEA, 8D, and first‑principles physics approaches.
• Flexibility: As per business needs, sometimes it is required to work during off‑hour times and/or with CWW shift schedule.
• Familiar with Metrology Tools: Ellipsometry, SEM, and AFM for thickness and roughness check.
• Experience on Defect Reduction: Experience identifying killer defects and improving wafer yield.
• Basic Idea of Fab Integration: Understanding of how CMP affects following steps (Etch/Photo) and overall yield.
• DOE: Ability to run structured Design of Experiments for process optimization.

Responsibilities

• Removal Rate (RR) control: evaluating factors to ensure thickness consistency across wafers.
• Condition optimization: determining optimal process conditions to improve uniformity and resolve issues.
• Recipe management: developing and optimizing Recipe parameters to improve flatness.
• Defect & uniformity management: improving wafer uniformity and resolving defects.
• Consumable life cycle management: monitoring usage cycles of pads and slurry to stay within specs.
• Material evaluation: assessing slurries and polishing pads to optimize CMP.

Skills

Statistical Process Control (SPC)

Fault Detection and Classification (FD

Education

BS/MS in Chemical/Mechanical/Electrical/Industrial Engineering or Physical Sciences

Tools

AMAT/EBara CMP tools

End point systems

Ellipsometry

SEM

AFM

Job description

Samsung Austin Semiconductor is seeking a CMP Process Engineer to own critical planarization steps in a high-volume fab. You will control removal rate, optimize recipes, and manage defects to ensure wafer flatness and yield.

Experience with CMP tools and metrology, plus DOE for process optimization, is required. Join a team that analyzes materials, implements process improvements, and collaborates across fabs.