Senior CMP Process Engineer - Precision Wafer Flatness

Samsung Electronics; Taylor (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

Life insurance + 401(k) matching

Onsite café and workout facilities

Paid parental leave

Paid time off + holidays

Wellness incentives

Job summary

Samsung Austin Semiconductor is seeking a CMP Process Engineer to drive wafer planarization, control removal rates, and optimize CMP recipes. You will work with CMP tools, analyze SPC/FDC data, and address defects to ensure high wafer yield and process stability.

The role requires hands-on experience with CMP equipment, strong problem-solving skills, and flexibility to cover shifts as needed in a fast-paced semiconductor manufacturing environment.

Qualifications

• BasicCMPKnowledge: Understanding CMP fundamentals, slurry-pad conditioning, post-clean steps.
• Hands-on experience with major CMP tools: AMAT/EBara and endpoints systems.
• Proficiency in SPC, FDC, and analysis software like JMP or Spotfire.
• Root-cause analysis using FMEA, 8D, and first-principles physics approaches.
• Willingness to work off-hours and/or with CW shifts as needed.

Responsibilities

• RemovalRate control: evaluate factors to ensure thickness consistency across wafer.
• Condition optimization: determine process conditions to improve uniformity and resolve issues.
• Recipe management: develop and optimize recipe parameters to improve flatness.
• Defect and uniformity management: reduce defects and improve wafer uniformity.
• Consumable lifecycle management: monitor usage cycles to avoid spec breaches.
• Material evaluation: compare slurries and polishing pads to optimize CMP.

Skills

CMP knowledge

Equipment familiarity

SPC

FDC

Data analysis tools

Problem solving

Shift flexibility

Tools

AMAT/EBara tools

Job description

Samsung Austin Semiconductor is seeking a CMP Process Engineer to drive wafer planarization, control removal rates, and optimize CMP recipes. You will work with CMP tools, analyze SPC/FDC data, and address defects to ensure high wafer yield and process stability.

The role requires hands-on experience with CMP equipment, strong problem-solving skills, and flexibility to cover shifts as needed in a fast-paced semiconductor manufacturing environment.