CMP Process Engineer - Semiconductor Manufacturing Specialist

Samsung; Taylor (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical insurance

401(k) matching

Onsite facilities

Job summary

Samsung Austin Semiconductor seeks a CMP Process Engineer to control wafer planarization during chemical mechanical polishing. You will optimize recipes, monitor removal rate, and ensure flat wafer surfaces for subsequent chip layers. Strong CMP knowledge, data analysis skills, and experience with AMAT/EBara tools are required.

The role includes off-hour flexibility, defect reduction, and collaboration with cross-functional teams to maintain high yields in a high-volume fab.

Qualifications

• BS or MS in Chemical, Mechanical, Electrical, or Industrial Engineering, Physics, Chemistry, Material Science, or Computer Science.
• Minimum 5 years of related experience in semiconductor manufacturing.
• Experience in high-volume semiconductor environments preferred.
• Basic CMP knowledge including slurry-pad-conditioning and post-clean steps.
• Hands-on experience with major CMP tools (AMAT/EBara) and endpoint systems.
• Proficiency in SPC, FDC, and analysis tools (JMP/Spotfire).
• Strong problem solving with FMEA, 8D, and first-principles physics approaches.

Responsibilities

• Control Removal Rate consistency across wafers during CMP processes.
• Optimize process conditions to improve uniformity and address center low RR profiles.
• Develop and optimize CMP recipe parameters for flatness.
• Manage wafer defects and uniformity, reducing scratches and particles.
• Monitor consumables usage (pads, slurry) to stay within specs.
• Evaluate slurries and polishing pads to optimize CMP outcomes.

Skills

SPC

FDC

JMP

Spotfire

DOE

8D

Root-cause analysis

Education

BS/MS in Engineering/Physics/Caint Sci

Tools

AMAT/EBara equipment

Job description

Samsung Austin Semiconductor seeks a CMP Process Engineer to control wafer planarization during chemical mechanical polishing. You will optimize recipes, monitor removal rate, and ensure flat wafer surfaces for subsequent chip layers. Strong CMP knowledge, data analysis skills, and experience with AMAT/EBara tools are required.

The role includes off-hour flexibility, defect reduction, and collaboration with cross-functional teams to maintain high yields in a high-volume fab.