CMOS Yield & Defect Reduction Engineer

Analog Devices; Camas (WA); On-site; USD 75,000 - 103,000; Full time

Benefits offered by this job

Medical, vision and dental coverage

401k with company match

Paid vacation and holidays

Discretionary performance-based bonus

Job summary

Analog Devices, Inc. in Camas, WA, is seeking a Front-End Fab Quality engineer to own defect control across multiple semiconductor processes and drive yield improvement.

You will investigate defect excursions, analyze data, and coordinate cross-functional efforts to prevent inline excursions. Qualifications include a BS/MS in a technical field and 2+ years of defect reduction experience in CMOS/BiCMOS or bipolar processes, with strong analytical and communication skills.

Qualifications

• BS or MS in Electrical Engineering, Electronics, Chemical Engineering, Materials Science or related field.
• 2+ years of experience reducing defects and improving yield in CMOS/BiCMOS or bipolar tech.
• Strong communication and data-driven decision making.

Responsibilities

• Defect control ownership across multiple semiconductor process flows.
• Support defect excursion investigations with data pull, containment, and disposition.
• Execute defect reduction initiatives using Pareto and yield kill ratio analyses.
• Support metrology and inspection tool performance across AOI/SEM platforms.
• Collaborate cross-functionally to plan experiments and optimize processes.
• Analyze defect and yield data and present clear updates.

Skills

Defect reduction

Yield enhancement

Communication skills

Analytical problem solving

Statistical analysis

Education

Bachelor's or Master's in Electrical Engineering or related field

Tools

JMP

KLARITY ACE

KLARITY Defect

KLA/ONTO tools

PDF DataPower

Job description

Analog Devices, Inc. in Camas, WA, is seeking a Front-End Fab Quality engineer to own defect control across multiple semiconductor processes and drive yield improvement.

You will investigate defect excursions, analyze data, and coordinate cross-functional efforts to prevent inline excursions. Qualifications include a BS/MS in a technical field and 2+ years of defect reduction experience in CMOS/BiCMOS or bipolar processes, with strong analytical and communication skills.