Chip Design Flows Architect for AI-Driven EDA

Voltai; Palo Alto (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

Voltai is building world models and AI-driven design tools for semiconductor hardware. This role owns frontend to backend design flows and bridges industry EDA tools with Voltai's AI systems.

You will build and maintain RTL-to-GDSII flows, integrate EDA tools with AI pipelines, and support on-prem deployments at scale. Collaboration with ML researchers and customers is essential for success.

Qualifications

• 5+ years CAD/flow or methodology experience at a semiconductor/EDA company.
• Hands-on experience with Synopsys and Cadence tools.
• Strong Python and Tcl.
• Experience with LSF, Slurm, or similar compute farm infrastructure.
• Understanding of the RTL-to-GDSII flow.

Responsibilities

• Build RTL-to-GDSII design flows spanning RTL, synthesis, STA, place and route, and signoff.
• Integrate Synopsys/Cadence tools with Voltai's AI data pipelines.
• Build regression, tracking, and reporting infrastructure for design and verification.
• Manage EDA licenses, compute infra, and job scheduling at scale.
• Partner with ML researchers to generate and curate large-scale design data.
• Support customer deployments in locked-down on-prem environments.

Skills

CAD/flow experience

Python

Tcl

LSF/Slurm

RTL-to-GDSII

Synopsys Cadence tools

Job description

Voltai is building world models and AI-driven design tools for semiconductor hardware. This role owns frontend to backend design flows and bridges industry EDA tools with Voltai's AI systems.

You will build and maintain RTL-to-GDSII flows, integrate EDA tools with AI pipelines, and support on-prem deployments at scale. Collaboration with ML researchers and customers is essential for success.