AI-Driven Digital Design Flow Architect

NXP Semiconductors

San Diego (CA)

On-site

USD 180,000 - 240,000

Full time

14 days+
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Job summary

NXP Semiconductors is seeking a Digital Design Flow Architect to define and deploy a repeatable RTL-to-GDS end-to-end flow for advanced process technologies. You will lead the integration of AI-enabled debugging, design-space exploration, and automated analysis loops to drive PPA optimization.

The role requires hands-on leadership, deep EDA experience, and the ability to partner across design, CAD/methodology, foundry, and vendor teams to deploy scalable flows and governance across RTL-to-GDS

Qualifications

  • Bachelor’s degree in EE/CE/CS or related field required; MS/PhD preferred.
  • Experience leading end-to-end digital design flows from RTL to GDS.
  • Ability to set technical direction and influence senior stakeholders.

Responsibilities

  • Architect a modular RTL-to-GDS flow for synthesis, place-and-route, timing/power closure, and GDS delivery.
  • Enable AI-assisted debugging, design-space exploration, and automated analysis loops for EDA workflows.
  • Establish repeatable flow practices with standards, configurations, metrics, dashboards, and regression tests.
  • Deploy flows for new process technologies in partnership with design, CAD/methodology, foundry, and EDA vendors.
  • Improve productivity and PPA through automation and reusable methodologies.

Skills

RTL-to-GDS
AI workflow development
Scripting
EDA knowledge
flow architecture

Education

B.S. in Electrical/Computer Engineering/CS
MS or PhD preferred

Tools

Synopsys
Cadence
Siemens EDA

Job description

NXP Semiconductors is seeking a Digital Design Flow Architect to define and deploy a repeatable RTL-to-GDS end-to-end flow for advanced process technologies. You will lead the integration of AI-enabled debugging, design-space exploration, and automated analysis loops to drive PPA optimization.

The role requires hands-on leadership, deep EDA experience, and the ability to partner across design, CAD/methodology, foundry, and vendor teams to deploy scalable flows and governance across RTL-to-GDS

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